VLSI Front-End Design & Verification — 8-Week Training Plan

Linux role in VLSI
Filesystem hierarchy; absolute/relative paths
Files/directories; permissions
stdin/stdout; pipes and redirection

1. Navigation: pwd/cd/ls
2. Create project_workspace project tree
3. File create/copy/move/delete
4. cat/less/head/tail
5. chmod and permission practice

6. Build project_workspace for VLSI work
7. Batch-create files/directories
8. Search and organize files by extension
9. Reproduce project_workspace without notes

Fix 10 incorrect Linux commands
Prepare 30-command Linux reference sheet

grep/find/sort/uniq/diff/cut/tee
Processes: ps/top/jobs/bg/fg/kill/nohup
Environment variables and PATH
GVim modes, search/replace, tabs, splits, visual block

1. Extract ERROR/WARNING/PASS/FAIL from logs
2. Find .v/.sv/.log files
3. Compare RTL revisions with diff
4. Edit Verilog in GVim
5. Search/replace signal names

6. GVim split RTL/TB view
7. Multi-tab editing
8. Visual block column edits
9. Verilog indentation/syntax highlighting
10. Regression log filtering

Create .vimrc for RTL/DV work
Find and correct formatting errors in a sample RTL file

Bash variables/arguments
if/case/for/while
Functions and exit status
Environment setup; simulation scripts
Basic Makefile concept

1. hello.sh
2. Command-line argument handling
3. File existence check
4. Loop through .v files
5. PASS/FAIL log counter

6. run_sim.sh: compile/run/log
7. clean.sh
8. setup_env.sh
9. Timestamp regression outputs
10. Simple Makefile target flow

Debug a broken shell script
Create one-command simulation flow

Number systems and signed arithmetic
Boolean algebra and gates
Combinational logic
MUX/decoder/encoder/comparator
Adder/subtractor/parity

1. Number conversions
2. Two's complement
3. Boolean simplification
4. Half/full adder truth tables
5. 2:1/4:1 MUX

6. Decoder
7. Priority encoder
8. Comparator
9. Parity generator/checker
10. Paper-design 4-function ALU

Solve 10 logic design problems
Prepare equations and block diagram for 4-bit ALU

Latch/flip-flop/register/counter
Clock/reset; Moore/Mealy FSM
C++ variables, loops, functions, arrays, strings
References, pointers, classes, constructors, inheritance

1. DFF timing
2. Register/shift register
3. Counter
4. Moore vs Mealy sequence detector
5. C++ calculator
6. Array min/max

7. String handling
8. Function/reference/pointer exercises
9. Transaction class
10. Constructor
11. Base/derived transaction classes

Week-1 practical: Linux + GVim + C++
20-minute digital design quiz

Verilog module/ports/nets/variables
Operators and continuous assignment
Parameters; hierarchy and instantiation
Compilation and basic simulation flow

1. AND/OR/XOR/XNOR
2. NAND/NOR
3. Multi-gate module
4. Half adder
5. Full adder
6. Full adder using half adders

7. Half/full subtractor
8. 4-bit ripple adder
9. Parameterized N-bit adder
10. Comparator
11. Parity generator/checker

Fix syntax, width, port and undeclared-signal bugs
Write one parameterized arithmetic block

always blocks and blocking assignment
if/else, case/casez/casex
Complete assignments and latch avoidance
Combinational coding guidelines

1. 2:1 MUX with assign
2. 2:1 MUX with if
3. 2:1 MUX with case
4. 4:1/8:1 MUX
5. Decoder/DEMUX

6. Encoder/priority encoder
7. Binary↔one-hot
8. Min/max selector
9. Leading-one/zero detector
10. Population counter
11. Parameterized MUX

Debug missing default, incomplete assignment, bad slicing
Explain why each faulty block infers wrong hardware

Signed vs unsigned arithmetic
Carry/borrow/overflow
Logical/arithmetic shifts
ALU structure and flag generation

1. 4/8-bit adder
2. Carry-in adder
3. Add/sub block
4. Increment/decrement
5. Signed adder/comparator

6. Absolute value
7. Logical/arithmetic shifters
8. Rotator
9. Barrel shifter
10. 8-operation ALU
11. Flags: C/Z/N/V
12. Parameterized ALU

Debug overflow and signedness corner cases
Independent 16-bit ALU implementation

Clocked always blocks
Non-blocking assignment
Sync/async reset
Enable/load/clear patterns
Shift registers

1. DFF
2. Sync-reset DFF
3. Async-reset DFF
4. Enable DFF
5. 4/8-bit registers
6. Register with load/clear

7. SISO/SIPO/PISO/PIPO
8. Bidirectional shift register
9. Universal shift register
10. Toggle FF
11. Edge detector
12. Pulse generator/stretcher

Debug blocking/NBA misuse, reset polarity, clock edge
Waveform explanation exercise

Counter architectures
Modulo and terminal count
Timer/reload/timeout
Interrupt generation
Watchdog concept

1. Up/down/up-down counters
2. Enable/load counter
3. MOD-10/MOD-N
4. Ring/Johnson/Gray counters
5. Free-running/event counters

6. Clock divider
7. Programmable counter
8. One-shot timer
9. Periodic timer
10. Timeout generator
11. Timer IRQ
12. Watchdog timer

Week-2 coding assessment
Mini-project: programmable timer with IRQ

parameter/localparam
Functions and tasks
generate-for / generate-if
Hierarchical reusable RTL
Compile-time configuration

1. Parameterized adder/MUX/comparator
2. Parameterized register/counter
3. Arithmetic/parity functions
4. Stimulus task
5. Generate register bank

6. Generate adder array
7. Conditional generate
8. Multi-channel configurable design
9. WIDTH 8/16/32 reuse challenge
10. Parameter override at instantiation

Fix bad parameter widths and generate conditions
Create reusable RTL package folder

FSM partitioning
Moore/Mealy
State encoding
Illegal-state recovery
Control-path verification

1. 2-state/3-state FSM
2. Moore detector
3. Mealy detector
4. Overlap/non-overlap
5. Traffic controller
6. Pedestrian control

7. Vending machine
8. Door controller
9. Elevator controller
10. Washing controller
11. Command processor
12. Handshake/timeout/retry
13. One-hot vs binary FSM

Debug dead state, missing transition, lockup and reset-state bugs
Compare Moore vs Mealy waveforms

Register arrays; RAM/ROM models
Sync/async reads
Address decode and write enable
Config/status registers
W1C and sticky status concepts

1. Register array
2. 8×8 and 16×32 register files
3. ROM
4. Single-port RAM
5. Sync read RAM

6. Address/write-enable decode
7. Config/status/RO/WO/RW regs
8. W1C register
9. Sticky status
10. HW-set/SW-clear
11. Register bank integration

Debug address aliasing and W1C behavior
Mini-project: config/status register block

FIFO architecture
Read/write pointers
Full/empty/occupancy
Overflow/underflow
Parameterized depth/width

1. FIFO storage
2. Write pointer
3. Read pointer
4. Empty/full logic
5. Write/read operations
6. Simultaneous R/W

7. Occupancy count
8. Overflow/underflow
9. Almost-full/empty
10. Param width/depth
11. Complete synchronous FIFO
12. FIFO error/status flags

Debug pointer and full/empty off-by-one bugs
Independent configurable FIFO

Fixed-priority arbitration
Round-robin concept
IRQ edge/level behavior
Mask/status/clear/priority
Aggregation

1. 2/4-request arbiter
2. Fixed priority
3. Grant-hold logic
4. Round-robin exercise
5. Edge/level IRQ capture

6. Sticky IRQ
7. IRQ status/enable/mask/clear
8. Multi-source IRQ
9. Priority IRQ
10. IRQ aggregation
11. 4-source interrupt controller

Week-3 assessment: FIFO + FSM + IRQ debugging
Document register map for IRQ controller

Testbench architecture
DUT instantiation
Clock/reset generation
Tasks/functions
System tasks and waveform dumping

1. AND-gate TB
2. DUT instantiation
3. Parameterized clock
4. Reset task
5. Directed stimulus
6. Loop stimulus

7. Random stimulus
8. Driver task
9. Checker function
10. $display/$monitor/$strobe
11. $dumpfile/$dumpvars
12. PASS/FAIL counters

Fix race-prone stimulus timing
Create reusable TB skeleton

Expected-value generation
Reference model concept
Automatic checking
Boundary/corner testing
Result summaries

1. Self-check adder/MUX/comparator
2. ALU reference model
3. Counter/shift register checkers
4. Timer checker
5. FSM checker

6. Register-block checking
7. FIFO checker
8. Arbiter checker
9. IRQ controller checker
10. Auto summary TOTAL/PASS/FAIL/ERROR

Inject one DUT bug and prove checker catches it
Write test plan for timer or FIFO

Reusable tasks/functions
File I/O concepts
Memory initialization
Random seeds/repeat loops
Basic regression scripting

1. Task library
2. Stimulus vector loop
3. Read test vectors from file
4. Write results to file
5. Memory preload

6. Multi-test selection
7. Seeded random runs
8. Batch 10 simulations
9. Log naming
10. Regression summary extraction
11. Waveform-on-fail flow

Debug non-reproducible random failure using seed
Build 5-test mini regression

Compile/elaboration/simulation failures
X/Z propagation
Width/signedness issues
Race conditions
RTL vs TB root cause

1. Syntax bug
2. Port mismatch
3. Width mismatch
4. Signed arithmetic bug
5. Blocking/NBA bug
6. Missing combinational assignment

7. Reset polarity bug
8. Counter off-by-one
9. FSM lockup
10. Multiple driver
11. FIFO pointer bug
12. TB timing race
13. X-propagation analysis

For each failure: reproduce → log → waveform → root cause → patch → rerun
Prepare bug report with evidence

Verification planning
Requirements-to-tests mapping
Regression discipline
Review and coding quality

1. Integrate timer/register/IRQ blocks
2. Build top-level TB
3. Directed smoke tests
4. Negative tests
5. Boundary tests

6. Random test loop
7. Regression script
8. Waveform debug
9. Clean PASS/FAIL report
10. Code review and lint-style checklist

Week-4 practical assessment
Mini-project demonstration

Verilog vs SystemVerilog
2-state/4-state types
logic/bit/byte/int/longint
Packed/unpacked arrays
typedef

1. logic vs bit
2. 2-state vs 4-state behavior
3. Packed arrays
4. Unpacked arrays
5. Multi-dimensional arrays

6. typedef aliases
7. Signed data types
8. Casting exercises
9. String basics
10. Packet field representation

Debug type-width and cast issues
Convert a Verilog TB data model to SystemVerilog

Dynamic arrays
Queues
Associative arrays
Array methods
enum/struct/union
foreach

1. Dynamic allocate/resize
2. Queue push/pop/insert/delete
3. Queue search/sort
4. Associative address map
5. foreach loops

6. enum state/opcode
7. struct packet
8. union storage demo
9. Array reduction methods
10. Transaction queue
11. Scoreboard-style associative store

Debug out-of-range and empty-queue cases
Build packet database utility

Class/object/handle
Constructor and this
Methods
Object assignment
Copy/compare/print concepts

1. Basic packet class
2. Object creation
3. Constructor
4. this keyword
5. Display method
6. Copy method

7. Compare method
8. Object handle assignment
9. Null-handle handling
10. Array of objects
11. Queue of objects
12. Transaction utility class

Debug null handle and shallow copy issue
Build reusable transaction class

Inheritance
Polymorphism
Virtual methods/classes
local/protected/static
Parameterized classes
Composition

1. Base/read/write transactions
2. Override display/compare
3. Base handle + derived object
4. Virtual method demo
5. Static object counter

6. Protected/local members
7. Parameterized transaction
8. Class composition
9. Abstract-style base class exercise
10. Factory-like manual creation exercise
11. Deep-copy hierarchy

Debug slicing/override mistakes
Create extensible packet hierarchy

fork/join variants
Process synchronization
events
mailboxes
bounded mailbox
semaphore
Producer/consumer

1. fork...join
2. join_any
3. join_none
4. wait fork
5. disable fork
6. Event trigger/wait

7. Mailbox put/get/try_get
8. Bounded mailbox
9. Semaphore lock
10. Producer-consumer
11. Parallel stimulus
12. Timeout/watchdog process

Debug mailbox deadlock and runaway process
Week-5 assessment: OOP + IPC

interface
modport
clocking blocks
Virtual interface concept
Signal direction and sampling discipline

1. Basic interface
2. DUT connection
3. Driver modport
4. Monitor modport
5. Clocking block

6. Input/output skew experiment
7. Parameterized interface
8. Interface tasks
9. Multiple interface instances
10. Virtual-interface handle exercise
11. Race-free drive/sample

Debug wrong modport and clocking direction
Refactor raw-pin TB to interface-based TB

Transaction-based verification
Generator/driver/monitor
Scoreboard/reference model
Mailbox communication
Environment layering

1. Transaction class
2. Generator
3. Generator→driver mailbox
4. Driver
5. Monitor

6. Monitor→scoreboard path
7. Reference model
8. Actual/expected compare
9. Environment class
10. End-of-test statistics
11. Error injection
12. Complete ALU/FIFO environment

Debug a scoreboard mismatch
Draw and document TB architecture

rand/randc
Basic constraints
inside
Ranges and exclusions
Inline constraints
pre/post_randomize

1. Random address/data
2. rand vs randc
3. Range constraint
4. inside set
5. Exclusion constraint
6. Aligned address

7. Legal opcode
8. Boundary values
9. Inline constraint
10. pre_randomize
11. post_randomize
12. 1,000 transactions

Debug impossible constraint
Create constrained transaction generator

Conditional/implication constraints
dist
solve before
soft constraints
Array constraints
Constraint inheritance/control

1. Conditional constraint
2. Implication
3. Weighted dist
4. solve-before
5. soft constraint

6. Dynamic-array size constraint
7. Array element constraints
8. Unique values
9. Constraint inheritance
10. constraint_mode
11. random_mode
12. Error-traffic generation

Analyze 5 randomization failures
Build legal + illegal transaction profiles

Verification plan creation
Stimulus/checker separation
Random + directed blend
Regression and debug workflow

1. Select FIFO or timer DUT
2. Build interface
3. Transaction/generator/driver
4. Monitor/scoreboard

5. Directed tests
6. Random tests
7. Error tests
8. Boundary tests
9. 10-seed regression
10. Failure triage
11. Final report

Week-6 practical assessment
Peer review of architecture and code

Immediate vs concurrent assertions
Sequence/property
|-> and |=>
## delays
disable iff
Pass/fail reporting

1. Immediate check
2. Reset property
3. Known-value check
4. One-hot
5. Onehot0
6. Mutual exclusion

7. Req→ack same/next cycle
8. Response within N cycles
9. Stable data
10. Pulse-width check
11. Reset disables property
12. Simple sequence composition

Debug vacuous/incorrect property
Add 8 assertions to timer/FIFO

Repetition operators
throughout/within concepts
FSM and protocol checks
FIFO safety properties
Latency/error properties

1. Consecutive repetition
2. Non-consecutive repetition
3. FSM legal state
4. No-write-on-full
5. No-read-on-empty

6. FIFO count bounds
7. Timer timeout property
8. IRQ latency
9. IRQ clear behavior
10. Handshake ordering
11. Data stability under wait
12. Error recovery

Debug 6 intentionally wrong properties
Create assertion plan mapped to requirements

covergroup/coverpoint
Automatic/explicit bins
Range/wildcard/transition bins
Sampling
Coverage options

1. Basic covergroup
2. Data bins
3. Address bins
4. Opcode bins
5. Range bins
6. Boundary bins

7. Wildcard bins
8. Transition bins
9. Illegal bins
10. Ignore bins
11. Manual sample
12. Event-based sampling
13. Per-instance exercise

Find why expected bin is not hit
Create coverage model for ALU/FIFO

Cross coverage
Conditional coverage
Coverage holes
Constraint tuning
Coverage closure workflow
Coverage reporting

1. op×data cross
2. addr×op cross
3. state×event cross
4. FIFO occupancy coverage
5. IRQ coverage

6. Conditional iff coverage
7. Run random baseline
8. Identify holes
9. Modify constraints
10. Directed closure test
11. Re-run coverage
12. Closure report

Explain each uncovered bin and closure action
Target ≥ planned coverage threshold

Integrating interfaces/OOP/random/SVA/coverage
Regression architecture
Debug discipline
Requirements traceability

1. Integrate transaction TB
2. Add constrained random
3. Add assertions
4. Add functional coverage
5. Add scoreboard

6. 20-seed regression
7. Inject RTL bug
8. Detect via checker/SVA
9. Analyze coverage
10. Close hole
11. Generate final SV report

Week-7 assessment
Prepare architecture presentation

UVM architecture and hierarchy
uvm_object vs uvm_component
uvm_sequence_item
Factory registration
Phases and reporting

1. UVM hello
2. Sequence item
3. Factory registration
4. print/copy/compare
5. Basic component

6. build/connect/run/report phases
7. Hierarchy print
8. uvm_info/warning/error/fatal
9. Transaction field automation
10. Simple test/env hierarchy

Debug missing registration/phase issue
Create minimal compiling UVM testbench

Sequence/sequence item
Sequencer
Driver
start_item/finish_item
get_next_item/item_done
Sequence control

1. Directed sequence
2. Random sequence
3. Reset sequence
4. Boundary sequence
5. Error sequence

6. Stress sequence
7. Sequencer
8. Driver
9. seq_item_port connection
10. Drive DUT via virtual interface
11. 100/1000 item sequence
12. Sequence reuse

Debug sequence not starting / item_done hang
Create sequence library

Monitor and analysis ports
Active/passive agent
Scoreboard/reference model
Environment and test
Analysis connectivity

1. Monitor
2. Analysis port
3. Scoreboard
4. Expected model
5. Compare actual/expected

6. Active agent
7. Passive agent
8. Agent config
9. Environment
10. Test class
11. Error injection
12. Statistics/report phase

Debug disconnected analysis path
Build complete UVM agent + scoreboard

uvm_config_db
Virtual interface
Config objects
Factory overrides
Objections
Subscribers/coverage
Regression/debugging

1. config_db set/get
2. Virtual interface
3. Config object
4. Object override
5. Component override

6. Objections
7. Coverage subscriber
8. Assertions integration
9. Smoke/reset/boundary/random/error/stress tests
10. Regression script
11. Log triage
12. UVM debug cases

Debug null VIF, bad config_db, wrong override, scoreboard mismatch
Run multi-test regression

End-to-end requirements→RTL→verification
Design review and verification review
Regression sign-off mindset
Technical presentation/viva

1. Integrate configurable timer + register block + IRQ
2. UVM env hookup
3. Directed smoke/reset/register tests
4. Assertions

5. Random/boundary/error/stress tests
6. Functional coverage
7. Regression
8. Bug injection and debug
9. Coverage closure
10. Final results package

Final coding assessment + viva
Present architecture, tests, bugs, coverage and regression results