Week 4 · Assessment checkpoint

Verilog Verification

Self-checking TB/regression/debug

3.0 hDuration
100Marks
After Day 20Assessment checkpoint
Assessment timing: End of Week 4, after Day 20.
Workbook requirement

Primary deliverable

Automated testbench + report

Workbook expectation

Pass expectation

Finds injected bug

Assessment detail: Duration, marks, deliverable and pass expectation follow the Week 4 workbook. The question-level paper and rubric are authored for ASIC Campus from the completed Days 16–20 learning outcomes.
Before you start

Verilog Verification Instructions

  1. Duration: 3 hours. Total: 100 marks.
  2. Work individually inside project_workspace/week4_verilog_verification/assessment/.
  3. Use plain Verilog for the DUT and verification code; Week 5+ methodology is outside scope.
  4. The submitted verification environment must be self-checking and produce objective PASS/FAIL evidence.
  5. Retain exact compile/run commands, logs, reproducible seed/configuration and waveform evidence used for debugging.
  6. An injected DUT defect is part of the assessment. The verification environment must detect it before the learner repairs or isolates the defect.
  7. Submit a concise regression/debug report mapping requirements to tests, evidence and final closure status.
100-mark practical assessment

Assessment Questions & Practical Tasks

All tasks stay within the published Week 4 scope: Self-checking TB/regression/debug.

QUESTION 1

Reusable Testbench Architecture

DUT instantiation, clock/reset, reusable tasks/functions and deterministic stimulus
15 marks

Build the reusable top-level Verilog testbench skeleton for the supplied mini-system and prove deterministic reset plus smoke-test operation.

Requirements
  • Instantiate the supplied DUT correctly.
  • Generate parameterized clock and deterministic reset.
  • Use at least one reusable driver task and one checker/helper function.
  • Enable log and VCD evidence.
Evidence to submit

Testbench source, compile/run log and reset/smoke waveform evidence.

Marking

Architecture 6; clock/reset 4; reuse 3; evidence 2.

QUESTION 2

Self-Checking Reference Model and Boundaries

Expected-value generation, automatic checking and corner cases
20 marks

Add independent expected-value logic and automatic checking for the assigned functional block(s), including meaningful boundary and negative cases.

Requirements
  • Expected result is computed independently of DUT output.
  • Every required test updates TOTAL/PASS/FAIL or equivalent counters.
  • Include normal, boundary and negative cases.
  • Final result is machine-readable PASS/FAIL.
Evidence to submit

Checker/reference code, test list and self-checking result log.

Marking

Reference/checker 8; boundary/negative tests 6; automatic result accounting 4; evidence 2.

QUESTION 3

Reproducible Mini Regression

File-driven stimulus, seeded runs, batch execution and result summary
20 marks

Run a minimum five-test regression that includes file-driven and seeded stimulus, preserving enough information to reproduce any failure.

Requirements
  • Execute at least five named tests.
  • Use file-driven stimulus for at least one test.
  • Record the seed/configuration for pseudo-random testing.
  • Retain per-test logs and an aggregate regression summary.
  • Generate waveform evidence on failure.
Evidence to submit

Regression command/script, vectors, seed record, per-test logs and summary.

Marking

Regression execution 7; reproducibility 5; file/seed flow 4; reporting 4.

QUESTION 4

Injected-Bug Detection and Root Cause

Failure reproduction, waveform/log diagnosis and RTL-vs-TB root cause
25 marks

Use the verification environment to detect the supplied injected DUT defect, reproduce it, identify root cause, patch or isolate it, then rerun the focused test.

Requirements
  • The unmodified checker must expose the injected defect.
  • Record the failing test, seed/configuration and first useful failure message.
  • Use log and waveform evidence to classify RTL versus testbench root cause.
  • Document the minimal correction and why it is correct.
  • Show the focused test passing after correction without weakening the checker.
Evidence to submit

Before/after logs, waveform/debug evidence, root-cause note and patch/diff.

Marking

Bug detection 8; reproduction/evidence 5; root cause 6; correction/rerun 6.

QUESTION 5

Full Regression and Verification Closure Report

Requirements-to-tests mapping, final regression and closure
20 marks

Run the complete assessment regression after the debug correction and submit a concise verification closure report.

Requirements
  • Map each assessed requirement to one or more tests.
  • Run the full regression, not only the previously failing test.
  • Summarize TOTAL/PASS/FAIL and unresolved issues.
  • State final closure status with links/paths to supporting evidence.
Evidence to submit

Requirements-to-tests matrix, final regression summary and verification/debug report.

Marking

Traceability 6; full regression 6; closure evidence 5; report quality 3.

Submission checklist

Required evidence

  • project_workspace/week4_verilog_verification/assessment/
  • DUT/testbench/reference/checker source used for the assessment
  • Input vector/configuration files and reproducible seed record
  • Per-test logs plus final regression summary
  • Failure and post-fix waveform/debug evidence
  • Injected-bug root-cause note and patch/diff
  • Requirements-to-tests matrix and final verification closure report
  • README.md with exact compile/run/regression commands
Completion gate

Pass criteria

  • Total score meets the programme/instructor pass threshold.
  • Assessment sources compile and execute without manual source repair during evaluation.
  • The self-checking environment produces objective PASS/FAIL results.
  • The learner's verification detects the supplied injected DUT bug.
  • The failure is reproducible and supported by log/waveform evidence.
  • After correction, the focused test and complete regression pass without weakening the checker.
  • The closure report maps requirements to tests and retained evidence.
Assessment execution contract

2.5-hour submission structure

Workspace: project_workspace/week4_verilog_verification/assessment/

Recommended timebox
  1. 0–20 min: read requirements, inspect DUT, create workspace and verification plan.
  2. 20–65 min: Q1 reusable testbench architecture and deterministic smoke test.
  3. 65–105 min: Q2 independent checker plus boundary/negative tests.
  4. 105–130 min: Q3 five-test file/seed regression and summary.
  5. 130–165 min: Q4 injected-bug detection, reproduction, waveform diagnosis and correction.
  6. 165–180 min: Q5 full regression, requirements-to-tests matrix and closure packaging.
Final submission checklist
  • Q1–Q5 required files/evidence are present.
  • Five or more regression tests are represented in the retained evidence.
  • Seed/configuration needed to reproduce pseudo-random failures is recorded.
  • Injected-bug failure evidence predates the correction and is not fabricated by weakening the checker.
  • Focused post-fix rerun and full post-fix regression results are retained.
  • Requirements-to-tests and verification closure reports are complete.
  • README.md gives exact commands and expected output locations.
Q1 · 15 marks

Required files
  • tb/tb_top.v
  • logs/q1_smoke.log
  • waves/q1_smoke.vcd
Mandatory verification
    Marking rubric
      Q2 · 20 marks

      Required files
      • tb/checker.v
      • docs/test_plan.md
      • logs/q2_selfcheck.log
      Mandatory verification
        Marking rubric
          Q3 · 20 marks

          Required files
          • vectors/
          • scripts/run_regression.sh
          • logs/regression/
          • reports/q3_regression_summary.txt
          Mandatory verification
            Marking rubric
              Q4 · 25 marks

              Required files
              • logs/q4_fail.log
              • waves/q4_fail.vcd
              • reports/q4_root_cause.md
              • patches/q4_fix.diff
              • logs/q4_rerun.log
              Mandatory verification
                Marking rubric
                  Q5 · 20 marks

                  Required files
                  • reports/requirements_to_tests.md
                  • reports/final_regression.txt
                  • reports/verification_closure.md
                  Mandatory verification
                    Marking rubric
                      Regression commands
                      iverilog -g2012 -Wall -o sim/week4_assessment.vvp rtl/*.v tb/*.v
                      vvp sim/week4_assessment.vvp | tee logs/assessment_smoke.log
                      sh scripts/run_regression.sh | tee logs/full_regression.log
                      gtkwave waves/q4_fail.vcd
                      Assessment validity
                      • Assessment testbench cannot compile or execute.
                      • No objective self-checking PASS/FAIL evidence is submitted.
                      • The injected DUT bug is not detected by the learner's verification environment.
                      • The learner disables or weakens a checker merely to obtain PASS.
                      • No reproducible debug evidence or final regression result is submitted.
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