Verilog RTL I – Fundamentals

1. Create project_workspace/week2_verilog_rtl1/day6 with rtl, tb, sim and logs directories.
2. Use Icarus Verilog for compile/simulation and GTKWave for waveform inspection.
3. Keep one compile/run log for the final evidence.

1. Implement AND, OR, XOR, XNOR, NAND and NOR modules.
2. Implement half adder and full adder, then build a full adder hierarchically from half adders.
3. Implement half/full subtractor and a 4-bit ripple-carry adder.
4. Convert the adder into a parameterized N-bit module.
5. Implement comparator and parity generator/checker blocks.
6. Write a basic testbench that exercises nominal and boundary input combinations.

1. Explain the difference between a net and a procedural variable in Verilog.
2. Explain continuous assignment and when assign is appropriate.
3. Explain why explicit vector widths matter in arithmetic RTL.
4. Describe parameter elaboration and one benefit of parameterized RTL.
5. Draw the hierarchy of a full adder built from two half adders and identify all interconnect signals.

Repair instructor-provided syntax, port-map, undeclared-signal and width-mismatch defects, then explain each correction.

• RTL source files
• basic testbench
• compile/simulation log
• waveform or terminal result
• written answers

• All required modules compile without errors
• Testbench demonstrates correct arithmetic behavior
• Parameterized block works for at least two widths
• Learner can explain module/port/net/parameter choices

• rtl/gates.v
• rtl/half_adder.v
• rtl/full_adder.v
• rtl/ripple_adder.v
• rtl/adder_n.v
• rtl/comparator.v
• rtl/parity.v
• tb/tb_day6.v

• All basic gate truth-table combinations
• Half/full adder carry cases
• 4-bit ripple adder 0+0, 1+1, 15+1 and representative vectors
• Parameterized adder at two widths
• Comparator equal/less/greater cases
• Parity even/odd cases

• Testbench terminates with PASS
• No $fatal/$error
• Compile has no errors
• Required VCD and log exist