Week 3 · Day 12 · 7 hours

Verilog RTL II – FSM Intensive

Parameterization, FSM, memories, FIFO, arbiter, interrupts

Open supporting lesson → Week 3 assessment View in full programme
Daily plan

What you will learn and practise

Complete the stages in order and retain the requested evidence.

Theory · 2h

FSM partitioning
Moore/Mealy
State encoding
Illegal-state recovery
Control-path verification

Guided lab · 2h

1. 2-state/3-state FSM
2. Moore detector
3. Mealy detector
4. Overlap/non-overlap
5. Traffic controller
6. Pedestrian control

Independent lab · 2h

7. Vending machine
8. Door controller
9. Elevator controller
10. Washing controller
11. Command processor
12. Handshake/timeout/retry
13. One-hot vs binary FSM

Debug and assignment · 1h

Debug dead state, missing transition, lockup and reset-state bugs
Compare Moore vs Mealy waveforms

Expected deliverable

FSM portfolio + debug report

Practical work

Design, simulate and debug robust Moore and Mealy finite-state machines with explicit recovery behavior.

Setup
  1. Create project_workspace/week3_verilog_rtl2/day12_fsm with rtl, tb, sim and logs directories.
  2. Keep state diagrams/tables with the RTL evidence.
  3. Exercise reset and illegal/unexpected transition conditions.
Execution steps
  1. Implement 2-state and 3-state FSMs.
  2. Implement Moore and Mealy sequence detectors.
  3. Exercise overlap and non-overlap behavior.
  4. Implement traffic and pedestrian controllers.
  5. Implement selected vending/door/elevator/washing/command-control FSM exercises.
  6. Implement handshake/timeout/retry control.
  7. Compare one-hot and binary encoding on a selected FSM.
Written assignment
  1. Compare Moore and Mealy output behavior.
  2. Explain FSM partitioning into state register, next-state and output logic.
  3. Explain illegal-state recovery.
  4. Compare one-hot and binary state encoding.
  5. Describe how reset choice affects FSM startup behavior.
Debug challenge

Find and repair dead-state, missing-transition, lockup and reset-state bugs; compare Moore and Mealy waveforms.

Evidence to retain
  • FSM RTL
  • state diagram/table
  • testbench
  • waveforms
  • debug report
Completion criteria
  • FSMs reset to defined states
  • Expected transitions are demonstrated
  • Illegal/unexpected conditions recover as designed
Executable lab

Build, run and retain evidence

project_workspace/week3_verilog_rtl2/day12_fsm/

Required files
    Mandatory tests
      Compile
      Run
      Waveform
      PASS criteria
        Knowledge check

        Review before completing Day 12

        1. Concept

          What distinguishes Moore and Mealy FSM outputs?

          Review answer

          Moore outputs depend on the current state, while Mealy outputs can depend on both the current state and current inputs.

        2. RTL reasoning

          Why is a default next-state assignment useful at the beginning of combinational next-state logic?

          Review answer

          It gives defined behavior for paths not explicitly changing state and helps prevent unintended latches from incomplete assignment.

        3. Debugging

          An FSM reaches a state for which the case statement has no recovery path and remains stuck. What design feature is missing?

          Review answer

          A defined illegal/unexpected-state recovery path, normally returning the machine to a documented safe state.

        4. Short answer

          What evidence should be shown to prove overlap behavior in a sequence detector?

          Review answer

          Stimulus containing overlapping sequences together with state/output waveform or simulation results demonstrating that the detector recognizes the required overlapping occurrences.

        Skills and assessment traceability

          Assessment: