SystemVerilog Randomization II
Conditional/implication constraints
dist
solve before
soft constraints
Array constraints
Constraint inheritance/control
Concept and setup
Understand what you will build
Day 29 — Advanced SystemVerilog Constraints
Simulation status (28 Oct 2026): run_day29.sh builds and runs both testbenches on Verilator 5.052, and both pass, including all five UNSAT cases. On 24 Oct 2026 a variable named priority, a reserved word, was renamed prio. Verilator needs the z3 solver installed to run randomize(). Details: Week 6 validation record (VALIDATION.md).
- advanced_constraints.sv: if/else, implication, weighted dist, solve before, soft, dynamic arrays, foreach, ordered values, inheritance, constraint_mode, rand_mode, inline overrides and legal/illegal profiles.
- tb_unsat_cases.sv: five independent expected-unsatisfiable scenarios.
- LABS.md: 16 XLS-derived labs and evidence checklist.
- run_day29.sh: builds and runs both testbenches on Verilator 5 (with z3) and checks their PASS lines.
- Icarus Verilog 12 does not support these constraints; use Verilator 5 or a commercial simulator.
Constraint-debug checklist
| Symptom | First investigation |
|---|---|
randomize() returns zero |
Check whether base, inherited, and inline constraints can all hold at once. Reduce the object to the smallest failing field set. |
| A field appears biased | Review dist, conditional branches, and solve before; compare observed counts across a recorded seed set. |
| An array has an unexpected size or order | Check foreach index bounds, size constraints, and ordering relationships separately. |
| A derived class cannot produce a legal item | Inspect inherited constraints and whether constraint_mode() or rand_mode() changed the active set. |
| Failure disappears on another run | Preserve the seed and simulator version; do not treat a different random sequence as a fix. |
When a solver reports failure, preserve it as evidence and explain the contradiction. Do not weaken a constraint until the changed legal space has been compared with the requirements.
Architecture
Follow the verification data flow
Worked source
Study the supplied implementation
advanced_constraints.sv
// Day 29 advanced constraints. IEEE 1800 SystemVerilog; full constraint solver required.
class packet;
rand bit [7:0] addr;
rand bit [7:0] payload;
rand bit write_enable;
rand bit [1:0] kind;
rand bit [3:0] values[];
rand bit [3:0] prio;
bit error_mode = 0;
constraint size_c { values.size() inside {[3:5]}; }
constraint address_c {
if (write_enable) addr inside {[8'h20:8'h3f]};
else addr inside {[8'h00:8'h1f]};
}
constraint implication_c { (kind == 2) -> (payload == 8'hff); }
constraint weighted_c { kind dist {0 := 6, 1 := 3, 2 := 1}; }
constraint ordering_c {
foreach (values[i]) {
values[i] inside {[0:15]};
if (i > 0) values[i] > values[i-1];
}
}
constraint preferred_c { soft prio == 4'd3; }
constraint legal_c {
if (!error_mode) payload != 8'h00;
else payload == 8'h00;
}
// Demonstrate solve-before: this influences distribution, not correctness.
constraint solve_order_c { solve write_enable before addr; }
function void post_randomize();
if (values.size() < 3 || values.size() > 5)
$fatal(1, "size outside policy");
endfunction
endclass
class restricted_packet extends packet;
constraint subclass_c { prio inside {[1:7]}; addr != 8'h00; }
endclass
module tb_advanced_constraints;
packet p;
restricted_packet q;
int failures;
initial begin
p = new();
for (int i = 0; i < 100; i++) begin
if (!p.randomize()) $fatal(1, "legal randomize failed at %0d", i);
if (p.write_enable && !(p.addr inside {[8'h20:8'h3f]}))
$fatal(1, "write address illegal");
if (!p.write_enable && !(p.addr inside {[8'h00:8'h1f]}))
$fatal(1, "read address illegal");
if (p.kind == 2 && p.payload != 8'hff) $fatal(1, "implication broken");
if (p.payload == 0) $fatal(1, "legal profile produced error payload");
foreach (p.values[j])
if (j > 0 && p.values[j] <= p.values[j-1])
$fatal(1, "array not strictly ordered");
end
p.error_mode = 1;
// kind=2 forces payload FF, conflicting with error_mode payload 00.
if (p.randomize() with { kind == 2; })
$fatal(1, "expected UNSAT for conflicting illegal profile");
// Error traffic can be generated when kind is not 2.
if (!p.randomize() with { kind == 0; }) $fatal(1, "error profile UNSAT");
if (p.payload != 0) $fatal(1, "error profile incorrect");
p.error_mode = 0;
p.preferred_c.constraint_mode(0);
if (!p.randomize() with { prio == 9; })
$fatal(1, "disabled soft preference should allow override");
p.preferred_c.constraint_mode(1);
p.prio.rand_mode(0);
p.prio = 3;
if (!p.randomize()) $fatal(1, "rand_mode test failed");
if (p.prio != 3) $fatal(1, "rand_mode changed fixed field");
p.prio.rand_mode(1);
q = new();
if (!q.randomize()) $fatal(1, "inherited constraint UNSAT");
if (q.prio < 1 || q.prio > 7) $fatal(1, "inheritance violation");
$display("DAY29_PASS advanced constraints");
$finish;
end
endmodule
tb_unsat_cases.sv
// Five expected randomization failures: a failure to randomize is a PASS for each case.
class failure_case;
rand int unsigned x, y;
constraint base_c { x inside {[0:10]}; y inside {[0:10]}; }
endclass
module tb_unsat_cases;
failure_case p;
int detected = 0;
initial begin
p = new();
if (!p.randomize() with { x > 10; }) detected++; else $fatal(1,"case1 not detected");
if (!p.randomize() with { x < 0; }) detected++; else $fatal(1,"case2 not detected");
if (!p.randomize() with { x == 2; x == 3; }) detected++; else $fatal(1,"case3 not detected");
if (!p.randomize() with { x > y; y > x; }) detected++; else $fatal(1,"case4 not detected");
if (!p.randomize() with { x == 11; y == 11; }) detected++; else $fatal(1,"case5 not detected");
if (detected != 5) $fatal(1,"not all failures detected");
$display("DAY29_UNSAT_PASS %0d cases", detected);
$finish;
end
endmodule
Guided and independent work
Complete the lab checklist
Day 29 — XLS Lab Inventory
- [ ] Lab 1 — Conditional constraint: Code and demonstrate conditional constraint with simulation evidence; document observations or debug result.
- [ ] Lab 2 — Implication constraint: Code and demonstrate implication constraint with simulation evidence; document observations or debug result.
- [ ] Lab 3 — Weighted dist: Code and demonstrate weighted dist with simulation evidence; document observations or debug result.
- [ ] Lab 4 — solve...before: Code and demonstrate solve...before with simulation evidence; document observations or debug result.
- [ ] Lab 5 — soft constraint: Code and demonstrate soft constraint with simulation evidence; document observations or debug result.
- [ ] Lab 6 — Dynamic-array size constraint: Code and demonstrate dynamic-array size constraint with simulation evidence; document observations or debug result.
- [ ] Lab 7 — Array element constraint: Code and demonstrate array element constraint with simulation evidence; document observations or debug result.
- [ ] Lab 8 — Unique array values: Code and demonstrate unique array values with simulation evidence; document observations or debug result.
- [ ] Lab 9 — Ordered values: Code and demonstrate ordered values with simulation evidence; document observations or debug result.
- [ ] Lab 10 — Constraint inheritance: Code and demonstrate constraint inheritance with simulation evidence; document observations or debug result.
- [ ] Lab 11 — Inline override: Code and demonstrate inline override with simulation evidence; document observations or debug result.
- [ ] Lab 12 — constraint_mode: Code and demonstrate constraint_mode with simulation evidence; document observations or debug result.
- [ ] Lab 13 — random_mode: Code and demonstrate random_mode with simulation evidence; document observations or debug result.
- [ ] Lab 14 — Legal traffic profile: Code and demonstrate legal traffic profile with simulation evidence; document observations or debug result.
- [ ] Lab 15 — Illegal traffic profile: Code and demonstrate illegal traffic profile with simulation evidence; document observations or debug result.
- [ ] Lab 16 — Random failure analysis: Code and demonstrate random failure analysis with simulation evidence; document observations or debug result.
The supplied examples run on Verilator 5.052 and cover the core topics; each of the 16 labs still needs your own evidence.
Assignment and evidence
Demonstrate the required engineering outcome
Debug assignment
Analyze 5 randomization failures
Build legal + illegal transaction profiles
Submission evidence
- Source files
- README with commands and environment
- Lab evidence log and screenshots if applicable
- Debug observations and outstanding issues
Review rubric
- Source and design
- 35
- Functional checks
- 30
- Debug and explanation
- 20
- Reproducibility
- 15
Personal evidence
This lesson is public; no account is needed to study it.
Knowledge check
Confirm the verification concepts
The scored check is being prepared.