Verilog RTL I – Counters/Timers

1. Create project_workspace/week2_verilog_rtl1/day10 and assessment subdirectories.
2. Define counter/timer requirements before implementation.
3. Use a self-checking testbench for the programmable timer.

1. Implement up, down and up/down counters.
2. Add enable/load and MOD-10/MOD-N behavior.
3. Implement ring, Johnson, Gray and free-running/event counters.
4. Implement clock-divider and programmable-counter exercises.
5. Implement one-shot and periodic timer behavior.
6. Implement timeout generation and timer IRQ.
7. Study watchdog behavior and implement the assigned watchdog exercise.
8. Complete the programmable timer with IRQ mini-project and self-checking testbench.

1. Explain terminal count and modulo behavior.
2. Compare free-running, one-shot and periodic timer operation.
3. Explain reload and timeout behavior for a programmable timer.
4. Describe when an interrupt should assert and how the testbench proves it.
5. Explain the purpose of a watchdog timer and what event normally prevents timeout.

Debug off-by-one terminal count, reload/timeout timing and interrupt assertion defects; preserve failing and corrected evidence.

• counter/timer RTL
• programmable timer + IRQ RTL
• self-checking TB
• waveform/log evidence
• written answers and debug report

• Counter boundaries and modulo wrap are correct
• Timer reload/timeout behavior matches specification
• IRQ timing is verified automatically
• Mini-project is ready for the Week 2 assessment

• rtl/counter.v
• rtl/mod_counter.v
• rtl/timer.v
• rtl/watchdog.v
• tb/tb_timer.v

• Counter wrap and terminal count
• Enable/load behavior
• MOD-N boundary
• One-shot expiry
• Periodic reload
• Timeout cycle
• IRQ assertion timing
• Watchdog kick before expiry and missing-kick timeout

• No off-by-one terminal-count failures
• Timer reload/timeout matches specification
• IRQ timing checked automatically
• Watchdog cases PASS
• Log and VCD retained