Verilog RTL I – Sequential

1. Create project_workspace/week2_verilog_rtl1/day9.
2. Use a repeatable clock/reset testbench.
3. Capture waveforms for reset, enable/load and normal operation.

1. Implement DFF, synchronous-reset DFF and asynchronous-reset DFF.
2. Implement enable DFF and 4/8-bit registers.
3. Implement register with load/clear.
4. Implement SISO, SIPO, PISO and PIPO shift registers.
5. Implement bidirectional and universal shift registers.
6. Implement toggle FF, edge detector and pulse generator/stretcher.
7. Verify reset and control priority using waveforms.

1. Why are nonblocking assignments preferred for clocked state updates?
2. Compare synchronous and asynchronous reset behavior.
3. Explain the effect of reset polarity and reset priority.
4. Describe load/enable/clear priority for a register specification.
5. From a supplied waveform, identify the sampling edge and explain the observed state transitions.

Repair blocking/nonblocking misuse, incorrect reset polarity and wrong clock-edge sensitivity, then compare the corrected waveform.

• sequential RTL collection
• testbench
• annotated waveform screenshots/files
• debug notes
• written answers

• State changes only at intended clock events
• Reset behavior matches specification
• Control priority is verified
• Waveform explanation matches RTL semantics

• rtl/dff.v
• rtl/register.v
• rtl/shift_registers.v
• rtl/edge_pulse.v
• tb/tb_day9.v

• Synchronous and asynchronous reset behavior
• Enable hold/update
• Load/clear priority
• SISO/SIPO/PISO/PIPO multi-cycle movement
• Bidirectional/universal shift behavior
• Edge detector/pulse timing

• State changes only as specified
• Reset/control priority checks PASS
• No compile errors
• Waveform shows required clock-edge evidence