Week 2 · Day 8 · 7 hours

Verilog RTL I – Arithmetic/ALU

Combinational, arithmetic, sequential, counters, timers

Open supporting lesson → Week 2 assessment View in full programme

Daily plan

What you will learn and practise

Complete the stages in order and retain the requested evidence.

Theory · 2h

Signed vs unsigned arithmetic
Carry/borrow/overflow
Logical/arithmetic shifts
ALU structure and flag generation

Guided lab · 2h

1. 4/8-bit adder
2. Carry-in adder
3. Add/sub block
4. Increment/decrement
5. Signed adder/comparator

Independent lab · 2h

6. Absolute value
7. Logical/arithmetic shifters
8. Rotator
9. Barrel shifter
10. 8-operation ALU
11. Flags: C/Z/N/V
12. Parameterized ALU

Debug and assignment · 1h

Debug overflow and signedness corner cases
Independent 16-bit ALU implementation

Expected deliverable

16-bit parameterized ALU + tests

Practical work

Design arithmetic RTL and a parameterized ALU with correct signedness, shifts and C/Z/N/V flag behavior.

Setup

Create project_workspace/week2_verilog_rtl1/day8.
Use explicit widths and signed declarations where the specification requires them.
Prepare directed corner-case vectors before coding the final ALU.

Execution steps

Implement 4-bit and 8-bit adders plus carry-in addition.
Implement add/subtract and increment/decrement blocks.
Implement signed adder/comparator and absolute-value logic.
Implement logical/arithmetic shifters and rotator/barrel shifter.
Implement an 8-operation ALU.
Generate carry, zero, negative and overflow flags.
Generalize the ALU by WIDTH parameter and verify a 16-bit instance.

Written assignment

Explain signed versus unsigned comparison with one bit-pattern example.
Differentiate carry and signed overflow.
Derive the signed-add overflow condition.
Explain logical versus arithmetic right shift.
For C/Z/N/V, state exactly when each ALU flag is asserted.

Debug challenge

Find and correct signedness, extension and overflow defects using boundary values such as maximum positive, minimum negative, zero and all-ones.

Evidence to retain

parameterized ALU RTL
directed testbench
corner-case results
C/Z/N/V evidence
written derivations/explanations

Completion criteria

16-bit ALU compiles and simulates
All specified operations pass directed tests
Flags are correct at arithmetic boundaries
Signed/unsigned behavior is explained correctly

Executable lab

Build, run and retain evidence

project_workspace/week2_verilog_rtl1/day8_alu/

Required files

rtl/addsub.v
rtl/shifter.v
rtl/alu.v
tb/tb_alu.v

Mandatory tests

Every ALU opcode
0+0 and maximum+1 carry
Positive and negative signed-overflow boundaries
Signed comparison
Logical versus arithmetic right shift with MSB=1
C/Z/N/V checked independently
16-bit parameterized instance

Compile

iverilog -g2012 -Wall -o sim/day8.vvp rtl/*.v tb/tb_alu.v

Run

vvp sim/day8.vvp | tee logs/day8_alu.log

Waveform

gtkwave sim/day8_alu.vcd

PASS criteria

All ALU operations PASS
C/Z/N/V boundary checks PASS
No compile errors
Directed test log and VCD retained

Knowledge check

Review before completing Day 8

MCQ
Which flag indicates that a signed arithmetic result cannot be represented in the destination width?
Review answer
Overflow (V).
Code reading
Why can carry and signed overflow have different values for the same addition?
Review answer
Carry describes unsigned extension; overflow describes signed representability.
Debug
An arithmetic right shift behaves like a logical shift. What declaration should you inspect first?
Review answer
Whether the shifted operand is declared/treated as signed.
Short answer
State the usual meanings of Z and N flags.
Review answer
Z means result is zero; N reflects the result sign/MSB under the defined convention.

Skills and assessment traceability

Arithmetic / ALU

signed/unsigned
carry/overflow
shifts
ALU operations
C/Z/N/V flags

Assessment: Q3