ASIC Campus Learning Hub

Complete ASIC design and verification learning path

Follow 40 structured training days from Linux and digital fundamentals through Verilog RTL, SystemVerilog verification, assertions, functional coverage and UVM. Every week now has active learning material, practical work and an assessment brief.

Open complete programme →Knowledge checksChoose a weekSearch references
8Active weeks
40Training days
42Published modules
59Published foundation lessons
01LearnUnderstand the engineering concept
→
02StudyRead the worked implementation
→
03PracticeComplete the guided lab
→
04DebugInvestigate incorrect behavior
→
05ReviewRetain evidence and assess
Current programme

Eight active weeks, in engineering order

Start from Week 1 when the flow is new. Experienced engineers can enter the week matching their current role and review earlier prerequisites when needed.

WEEK 01Available

Foundation

Linux, GVim, Shell, Digital Design, Basic C++

Days
1–5
Practice
Tool fluency + design fundamentals
WEEK 02Available

Verilog RTL I

Combinational, arithmetic, sequential, counters, timers

Days
6–10
Practice
Heavy RTL coding
WEEK 03Available

Verilog RTL II

Parameterization, FSM, memories, FIFO, arbiter, interrupts

Days
11–15
Practice
Reusable ASIC-style RTL
WEEK 04Available

Verilog Verification

Testbenches, self-checking, regression, debugging

Days
16–20
Practice
Verification + waveform debug
WEEK 06Available

SystemVerilog Verification

Interfaces, TB architecture, constraints

Days
26–30
Practice
Transaction-based verification
WEEK 07Staged review

SVA & Coverage

Assertions, functional coverage, closure

Days
31–35
Practice
Coverage-driven verification
Learning portal in staged review
WEEK 08Staged review

UVM & Final Integration

UVM components, advanced UVM, regression, final project

Days
36–40
Practice
Reusable methodology
Learning portal in staged review
Core references

Reference courses for core concepts

Use these eight focused references alongside the daily programme, from Linux and editor skills through RTL, SystemVerilog, UVM and EDA automation.

Week 1 · Days 1–3

Linux Fundamentals for ASIC Engineers

Use the filesystem, core commands, permissions, processes and an ASIC project workspace with confidence.

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Available15 detailed lessons
Week 1 · Day 2

Vi, Vim, GVim and Nano Editors

Edit RTL and testbench files using modes, navigation, search, replace, splits, tabs and practical project workflows.

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AvailableEditor reference
Week 1 · Days 4–5

Digital Design Fundamentals

Build the logic foundation for number systems, Boolean algebra, combinational circuits, sequential circuits and FSMs.

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Available11 detailed lessons
Weeks 2–4 · Days 6–20

Verilog RTL Design and Verification

Develop synthesizable RTL, reusable testbenches, self-checking verification, regression and waveform debugging skills.

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Available15 training days
Week 1 · Day 5

C++ Concepts Needed for SystemVerilog

Learn the focused C++ concepts that support SystemVerilog OOP: classes, constructors, inheritance, references and pointers.

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AvailableFocused language bridge
Weeks 5–7 · Days 21–35

SystemVerilog Design and Verification

Study data types, collections, OOP, concurrency, interfaces, constraints, assertions, functional coverage and layered testbenches.

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Available12 detailed lessons
Weeks 1–4 · Days 2–20

Scripting for EDA Automation

Automate compilation, simulation, log checking, regressions and synthesis with Bash, Make, Python and Tcl, and maintain csh setups and Perl flows.

Open reference →
Available11 detailed lessons
Recommended start

Build the foundation before advanced verification.

Begin with Linux, editors and digital logic. Continue through RTL coding and testbenches before moving into constrained random verification, assertions, coverage and UVM.

Foundation→RTL→SystemVerilog→UVM