Week 3 · Assessment checkpoint

Verilog RTL II

FSM/FIFO/register/interrupt

3.0 hDuration
100Marks
After Day 15Assessment checkpoint
Assessment timing: End of Week 3, after Day 15.
Workbook requirement

Primary deliverable

Advanced RTL block + debug evidence

Workbook expectation

Pass expectation

Correct function + clean coding

Assessment detail: Practical assessment authored from the published weekly curriculum and engineering deliverables.
Workspace: project_workspace/week3_verilog_rtl2/assessment/
Before you start

Verilog RTL II Instructions

  1. Complete the weekly lessons and executable labs before starting.
  2. Keep RTL, testbench, logs, waveform evidence and engineering notes in the specified workspace.
  3. Use reproducible compile and simulation commands and retain PASS/FAIL evidence.
  4. Complete the work independently and explain every submitted design and debug decision.
100-mark practical assessment

Assessment Questions & Practical Tasks

All tasks stay within the published Week 3 scope: FSM/FIFO/register/interrupt.

QUESTION Q1

Reusable RTL and Parameterization

15 marks

Repair and complete a configurable RTL block so that it operates correctly at multiple widths and uses safe parameter/localparam and generate practices.

Requirements
  • Compile at WIDTH 8, 16 and 32.
  • Remove fixed-width assumptions.
  • Explain one parameter/localparam choice and one generate/reuse choice.
  • Provide simulation evidence for all required widths.
Evidence to submit
  • q1/q1_answers.md
  • q1/reusable_block.v
  • q1/tb_q1.v
Marking

Marks are awarded for correct implementation, verification evidence, reproducibility and technical explanation.

QUESTION Q2

FSM Design and Debug

20 marks

Implement or repair the supplied control FSM from the stated behavior and demonstrate correct reset, transitions, outputs and recovery.

Requirements
  • Document state behavior.
  • Exercise all required transitions.
  • Demonstrate reset behavior.
  • Find/fix the injected transition or recovery defect.
  • Explain whether the implemented outputs are Moore or Mealy and why.
Evidence to submit
  • q2/fsm_controller.v
  • q2/tb_fsm_controller.v
  • q2/fsm_notes.md
Marking

Marks are awarded for correct implementation, verification evidence, reproducibility and technical explanation.

QUESTION Q3

Configuration / Status Register Block

20 marks

Implement a small register block containing documented RW/RO/status behavior, including W1C or sticky status semantics.

Requirements
  • Implement address decode.
  • Demonstrate RW readback and RO protection.
  • Demonstrate W1C/sticky behavior.
  • Avoid address aliasing.
  • Document the register map and HW/SW behavior.
Evidence to submit
  • q3/register_block.v
  • q3/tb_register_block.v
  • q3/register_map.md
Marking

Marks are awarded for correct implementation, verification evidence, reproducibility and technical explanation.

QUESTION Q4

Synchronous FIFO

25 marks

Implement or complete a parameterized synchronous FIFO and prove correct data ordering and boundary/status behavior.

Requirements
  • Verify reset/empty.
  • Fill exactly to full.
  • Preserve FIFO ordering.
  • Exercise simultaneous read/write.
  • Exercise pointer wraparound.
  • Demonstrate overflow/underflow handling.
  • Find/fix the supplied pointer/full-empty defect.
Evidence to submit
  • q4/sync_fifo.v
  • q4/tb_sync_fifo.v
  • q4/fifo_debug.md
Marking

Marks are awarded for correct implementation, verification evidence, reproducibility and technical explanation.

QUESTION Q5

Arbiter / Interrupt Controller

20 marks

Implement or repair a multi-source interrupt controller with deterministic priority and correct pending/mask/clear behavior.

Requirements
  • Support four interrupt sources.
  • Demonstrate simultaneous-source priority.
  • Demonstrate mask/enable behavior.
  • Clear one source without losing unrelated pending sources.
  • Verify aggregate IRQ behavior.
  • Document status/mask/clear behavior.
Evidence to submit
  • q5/irq_controller.v
  • q5/tb_irq_controller.v
  • q5/irq_register_map.md
Marking

Marks are awarded for correct implementation, verification evidence, reproducibility and technical explanation.

Submission checklist

Required evidence

  • Submit the complete project_workspace/week3_verilog_rtl2/assessment/ directory.
  • Include all required RTL and testbench files for Q1–Q5.
  • Include requested Markdown design/debug/register-map notes.
  • Include compile/run logs and waveform or equivalent simulation evidence.
  • All submitted work must be reproducible with the documented Icarus Verilog flow.
Completion gate

Pass criteria

  • Q1: reusable configuration and width safety — 15 marks.
  • Q2: FSM correctness and debugging — 20 marks.
  • Q3: register access/status semantics — 20 marks.
  • Q4: FIFO correctness and boundary/debug behavior — 25 marks.
  • Q5: interrupt/priority/mask/clear behavior — 20 marks.
  • Total — 100 marks.
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