Week 3 · Day 14 · 7 hours

Verilog RTL II – FIFO

Parameterization, FSM, memories, FIFO, arbiter, interrupts

Open supporting lesson → Week 3 assessment View in full programme
Daily plan

What you will learn and practise

Complete the stages in order and retain the requested evidence.

Theory · 2h

FIFO architecture
Read/write pointers
Full/empty/occupancy
Overflow/underflow
Parameterized depth/width

Guided lab · 2h

1. FIFO storage
2. Write pointer
3. Read pointer
4. Empty/full logic
5. Write/read operations
6. Simultaneous R/W

Independent lab · 2h

7. Occupancy count
8. Overflow/underflow
9. Almost-full/empty
10. Param width/depth
11. Complete synchronous FIFO
12. FIFO error/status flags

Debug and assignment · 1h

Debug pointer and full/empty off-by-one bugs
Independent configurable FIFO

Expected deliverable

Synchronous FIFO + status/error logic

Practical work

Build a configurable synchronous FIFO with correct pointer, occupancy, full/empty and error/status behavior.

Setup
  1. Create project_workspace/week3_verilog_rtl2/day14_fifo with rtl, tb, sim and logs directories.
  2. Use one clock domain only for this Week 3 FIFO.
  3. Exercise reset, empty, full, simultaneous read/write and boundary conditions.
Execution steps
  1. Implement FIFO storage.
  2. Implement write and read pointers.
  3. Implement empty/full logic.
  4. Implement write/read operations and simultaneous R/W.
  5. Add occupancy count.
  6. Add overflow and underflow detection.
  7. Add almost-full/almost-empty status.
  8. Parameterize width and depth.
  9. Integrate the complete synchronous FIFO and error/status flags.
Written assignment
  1. Explain the relationship between pointers and FIFO occupancy.
  2. Explain full and empty boundary conditions.
  3. Describe overflow and underflow handling.
  4. Explain simultaneous read/write behavior.
  5. Identify common FIFO off-by-one errors.
Debug challenge

Repair pointer and full/empty off-by-one defects and show the corrected boundary waveforms.

Evidence to retain
  • FIFO RTL
  • testbench
  • boundary-condition results
  • waveform
  • debug notes
Completion criteria
  • Empty/full behavior is correct
  • Overflow/underflow are handled
  • Parameterized FIFO passes configured-depth tests
Executable lab

Build, run and retain evidence

project_workspace/week3_verilog_rtl2/day14_fifo/

Required files
    Mandatory tests
      Compile
      Run
      Waveform
      PASS criteria
        Knowledge check

        Review before completing Day 14

        1. Concept

          What conditions do FIFO full and empty represent?

          Review answer

          Empty means no valid queued entries are available to read; full means no free FIFO entry is available for another valid write under the selected FIFO architecture.

        2. RTL reasoning

          For a valid simultaneous read and write on a synchronous FIFO, what normally happens to occupancy?

          Review answer

          Occupancy normally remains unchanged because one entry is removed while one entry is added, although both pointers advance.

        3. Debugging

          A FIFO asserts full one entry too early. What class of defect should be investigated first?

          Review answer

          An off-by-one error in full detection, occupancy comparison, pointer comparison or configured depth handling.

        4. Short answer

          Which boundary tests are essential before declaring a synchronous FIFO complete?

          Review answer

          Reset/empty, fill-to-full, overflow attempt, ordered reads, simultaneous read/write, pointer wraparound, drain-to-empty and underflow attempt.

        Skills and assessment traceability

          Assessment: