A practical SystemVerilog course for building class-based, constrained-random testbenches with interfaces, assertions and functional coverage, using open-source simulators.
Designed for: Students, fresh graduates and engineers moving from Verilog RTL into design verification
Verilog RTL Design and the C++ concepts bridge (Week 1, Day 5)
Progress through focused modules, technical lessons and practice checks in sequence.
Four-state and two-state types, packed and unpacked arrays, typedef, enum, struct, casting and strings.
Choosing and using dynamic arrays, queues and associative arrays, foreach, and the built-in array methods.
Class properties and methods, constructors, handles, null, shallow and deep copy, static members and this.
extends and super, virtual methods, $cast, abstract classes, pure virtual methods and parameterised classes.
fork and join variants, disable fork, named events, semaphores and mailboxes for coordinating testbench threads.
Interfaces, modports, clocking blocks, skews and virtual interfaces for connecting classes to the DUT.
Transaction, generator, driver, monitor, scoreboard, environment and test classes connected with mailboxes.
rand and randc, constraint blocks, randomize() with, pre_randomize and post_randomize, and seeds.
dist, implication, solve-before, soft constraints, constraint_mode, rand_mode and array constraints.
Immediate and concurrent assertions, sequences, implication, sampled-value functions, disable iff, cover and bind.
Covergroups, coverpoints, bins, illegal and ignore bins, cross coverage, sampling and coverage closure.
A complete FIFO environment with constrained stimulus, a reference model, assertions, coverage, regression and sign-off evidence.
The instructor-led plan covers the SystemVerilog language in Week 5, verification environments in Week 6, and assertions and functional coverage in Week 7, before UVM in Week 8.