Foundation Assessment
Linux/GVim/Shell + Digital + C++
- Duration
- 2.0 h
- Marks
- 100
- Primary deliverable
- Scripts + C++ transaction class
- Pass expectation
- Functional output + basic explanation
Assignments are part of the engineering flow.
Each weekly assessment checks the practical skills developed during that stage. All eight weekly briefs and their required deliverables are available for study and practice.
Verilog RTL I
Combinational/sequential/ALU/timer
- Duration
- 2.5 h
- Marks
- 100
- Primary deliverable
- RTL + TB + waveform
- Pass expectation
- Compiles, simulates, handles corner cases
Verilog RTL II
FSM/FIFO/register/interrupt
- Duration
- 3.0 h
- Marks
- 100
- Primary deliverable
- Advanced RTL block + debug evidence
- Pass expectation
- Correct function + clean coding
Verilog Verification
Self-checking TB/regression/debug
- Duration
- 3.0 h
- Marks
- 100
- Primary deliverable
- Automated testbench + report
- Pass expectation
- Finds injected bug
SV Language/OOP
Collections/OOP/processes/IPC
- Duration
- 2.5 h
- Marks
- 100
- Primary deliverable
- Transaction/OOP exercise
- Pass expectation
- Correct object behavior + concurrency
SV Verification
Interface/TB/constraints
- Duration
- 3.0 h
- Marks
- 100
- Primary deliverable
- Complete SV environment
- Pass expectation
- Directed + random verification
SVA/Coverage
Properties/coverage/closure
- Duration
- 3.0 h
- Marks
- 100
- Primary deliverable
- SVA + coverage closure report
- Pass expectation
- Meaningful checks + closure reasoning
UVM + Final
Complete UVM environment + final project
- Duration
- Full day
- Marks
- 200
- Primary deliverable
- Code + regression + presentation
- Pass expectation
- End-to-end demonstration
Final evaluation
How the complete programme is evaluated
20%Daily Labs
15%Weekly Assessments
15%RTL Coding
15%Verification Coding
10%Debugging Ability
20%Final Project
5%Technical Viva
100%Total
Final integrated project
Configurable Timer + Reg Block + IRQ
RTL
Register interface; timer/counter; interrupt logic; status/clear logic; integration
Verification
UVM agent/env; scoreboard/reference model; sequences/tests; random/boundary/error/stress regression
Sign-off evidence
Regression summary; assertions result; functional coverage; coverage closure; PASS/FAIL report; final sign-off package
Presentation / viva
Architecture; test strategy; bugs found; debug examples; lessons learned; viva
The UVM-based final project is active as the Week 8 integration stage. Complete the earlier weeks before attempting the full regression and sign-off package.