Week 3 · Day 15 · 7 hours

Verilog RTL II – Arbiter/Interrupt

Parameterization, FSM, memories, FIFO, arbiter, interrupts

Open supporting lesson → Week 3 assessment View in full programme
Daily plan

What you will learn and practise

Complete the stages in order and retain the requested evidence.

Theory · 2h

Fixed-priority arbitration
Round-robin concept
IRQ edge/level behavior
Mask/status/clear/priority
Aggregation

Guided lab · 2h

1. 2/4-request arbiter
2. Fixed priority
3. Grant-hold logic
4. Round-robin exercise
5. Edge/level IRQ capture

Independent lab · 2h

6. Sticky IRQ
7. IRQ status/enable/mask/clear
8. Multi-source IRQ
9. Priority IRQ
10. IRQ aggregation
11. 4-source interrupt controller

Debug and assignment · 1h

Week-3 assessment: FIFO + FSM + IRQ debugging
Document register map for IRQ controller

Expected deliverable

4-source interrupt controller + assessment

Practical work

Implement arbitration and a four-source interrupt controller with mask, status, clear and priority behavior.

Setup
  1. Create project_workspace/week3_verilog_rtl2/day15_arbiter_irq with rtl, tb, sim and logs directories.
  2. Document the IRQ controller register map.
  3. Test simultaneous requests/interrupts and masking/clearing behavior.
Execution steps
  1. Implement 2-request and 4-request arbitration.
  2. Implement fixed-priority and grant-hold behavior.
  3. Exercise round-robin arbitration.
  4. Implement edge and level IRQ capture.
  5. Implement sticky IRQ behavior.
  6. Implement IRQ status, enable, mask and clear.
  7. Aggregate multiple interrupt sources.
  8. Implement priority IRQ selection.
  9. Integrate a four-source interrupt controller.
Written assignment
  1. Explain fixed-priority arbitration.
  2. Describe the purpose of grant-hold behavior.
  3. Compare edge-triggered and level-sensitive interrupt capture.
  4. Explain IRQ status, enable, mask and clear.
  5. Explain how simultaneous interrupt sources are prioritized and aggregated.
Debug challenge

Perform the workbook Week 3 FIFO/FSM/IRQ debugging exercise and document the IRQ register map.

Evidence to retain
  • Arbiter RTL
  • interrupt-controller RTL
  • testbench
  • IRQ register map
  • debug evidence
Completion criteria
  • Arbitration is deterministic
  • Mask/status/clear behavior is correct
  • Four-source IRQ controller demonstrates simultaneous-source behavior
Executable lab

Build, run and retain evidence

project_workspace/week3_verilog_rtl2/day15_arbiter_irq/

Required files
    Mandatory tests
      Compile
      Run
      Waveform
      PASS criteria
        Knowledge check

        Review before completing Day 15

        1. Concept

          How does fixed-priority arbitration differ from round-robin arbitration?

          Review answer

          Fixed priority always prefers requests according to a fixed ordering; round-robin changes the starting priority over time so repeated service opportunities can be distributed among requesters.

        2. RTL reasoning

          Why are sticky pending bits useful for short interrupt events?

          Review answer

          They retain evidence of an event after the source pulse disappears, allowing software or downstream control to observe and explicitly clear the pending interrupt.

        3. Debugging

          Clearing IRQ source 0 also clears unrelated pending source 2. What behavior must be corrected?

          Review answer

          The clear logic must operate per source/bit so that acknowledging one interrupt does not erase other independently pending interrupts.

        4. Short answer

          What simultaneous-source behavior must be tested in a four-source interrupt controller?

          Review answer

          Multiple pending sources should preserve their individual status, obey enable/mask rules, produce the documented priority result and drive the aggregate IRQ correctly until the relevant pending conditions are cleared.

        Skills and assessment traceability

          Assessment:

          Weekly checkpoint

          Verilog RTL II

          3.0 h · 100 marks · Advanced RTL block + debug evidence

          Review Week 3 assignment →