Day 21 — SystemVerilog Data Types

Day 21 — SystemVerilog Language: Data Types

Simulation status (28 Oct 2026): The commands below pass on Icarus Verilog 12. Use Icarus for this day: Verilator 5.052 is two-state (X and Z become 0 or 1), so its run stops at the four-state check. Details: Week 5 validation record (VALIDATION.md).

Time: Theory 2 h + guided 2 h + independent 2 h + debug/assignment 1 h.

Workspace: project_workspace/week5_systemverilog/day21_data_types

Guided experiments (1–5)

1. logic vs bit initialization and X/Z behavior.
2. 2-state/4-state equality and case equality.
3. Packed vectors and bit selection.
4. Unpacked arrays and indexed access.
5. Multidimensional arrays.

Independent experiments (6–10)

1. typedef aliases.
2. Signed and unsigned values.
3. Width truncation and explicit casting.
4. string basics.
5. Typed packet fields.

Run and capture evidence

mkdir -p sim logs
iverilog -g2012 -Wall -o sim/day21.vvp tb/day21_types.sv
vvp sim/day21.vvp | tee logs/day21.log

These commands pass on Icarus Verilog 12. Record your simulator version with the log, and do not claim completion if compilation fails.

Debug task

Reproduce the deliberately wrong 4-bit cast of 8'hF3; explain the truncation and replace it with the intended width. Attach before/after values and PASS evidence. Convert a Verilog TB data model into typed SystemVerilog declarations.

Deliverable: SV datatype exercise set, log, debug note, and explanation of 2-state vs 4-state behavior.

Language boundary and package fundamentals

SystemVerilog extends Verilog; it does not make every construct synthesizable. Modules and a supported RTL subset describe hardware. Classes, constrained randomization, mailboxes, and covergroups are verification facilities. The extension .sv alone does not select a language version: use the simulator's SystemVerilog mode and record its version. Synthesis support still depends on the tool and the construct.

Choose a 4-state type such as logic for signals where x and z are useful debug evidence. A 2-state bit cannot preserve an unknown value; it is useful for testbench bookkeeping when unknown detection is not needed. Don't replace a DUT-facing logic signal with bit just to make an initialization warning disappear.

SystemVerilog also provides process forms that state the intended hardware:

These forms improve intent checking; they do not make incorrect logic correct, and support depends on the selected SystemVerilog mode and tool.

unique, unique0, and priority can document selection assumptions and enable run-time diagnostics. Use them only when the specification supports the assumption: unique expects exactly one matching choice, unique0 allows no match but expects at most one, and priority expects a matching choice. Keep safe defaults and explicit error behavior where required. Overlapping wildcard branches, unknown values, or a synthesis tool's optimization of assumed-unreachable cases can make an incorrect assumption costly; test those boundaries instead of treating the keyword as functional coverage.

A package gives related type and helper declarations a named scope. Compile the package before files that use it, then either qualify a name or import it:

package protocol_types;
  typedef enum logic [1:0] {IDLE, ACTIVE} state_t;
endpackage

module state_check;
  import protocol_types::*;
  state_t state;

  initial begin
    state = IDLE;
    if (state != IDLE) $fatal(1, "package type check failed");
    $display("PACKAGE_PASS");
    $finish;
  end
endmodule

The same type can be named as protocol_types::state_t when an explicit scope is clearer than importing all package names. Avoid broad wildcard imports from several packages when names may collide. A package is a compiled SystemVerilog construct, unlike a text include, which is expanded by the preprocessor.

Save the snippets in protocol_types.sv and state_check.sv, then run:

iverilog -g2012 -Wall -s state_check -o sim/package.vvp protocol_types.sv state_check.sv
vvp sim/package.vvp

Expected output is PACKAGE_PASS. If the selected tool rejects the construct, record that compatibility result; do not silently switch language modes.