Engineering learning pathVerilog RTL Design
A practical Verilog course for writing, simulating, debugging, and reviewing synthesizable RTL used in front-end ASIC and FPGA projects.
10Modules
10Lessons
350Learning minutes
4 weeksSuggested pace
OutcomesWhat you will be able to do
- Read and write Verilog confidently
- Model combinational and sequential hardware
- Use hierarchy, parameters, arrays, memories, tasks, functions, and generate constructs
- Explain simulation scheduling and race risks
- Build self-checking testbenches
- Review RTL for synthesis, lint, reset, width, latch, clock, and X-state problems
How to use this course
Know the outcome before you begin.
01UnderstandRead the objective and concept
→
02ApplyWork through examples and practice
→
03VerifyCheck the expected behaviour
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04ReviewUse knowledge checks to find gaps
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05AdvanceContinue only when the reasoning is clear
Completion expectationUnderstand the concept → apply it → inspect the result → explain why it is correct.
Curriculum
Course roadmap
Progress through focused modules, technical lessons and practice checks in sequence.
01How source code becomes simulated behavior and synthesized hardware.
- Verilog purpose and tool flow35 min
02Four-state values, nets, variables, literals, widths, signedness, and expression sizing.
- Values, types, expressions and operators35 min
03Reusable hardware boundaries, connectivity, parameterization, and elaboration.
- Modules, ports, hierarchy and parameters35 min
04Clear combinational coding with assign, always blocks, case statements, and complete assignment coverage.
- Continuous assignments and combinational RTL35 min
05Flip-flops, resets, enables, counters, shift registers, and finite-state machines.
- Clocked RTL, reset and finite-state machines35 min
06Packed vectors, unpacked memories, indexing, memory templates, loops, and generate blocks.
- Arrays, memories and generate constructs35 min
07Local computation, testbench procedures, constants, and disciplined preprocessor use.
- Tasks, functions and reusable definitions35 min
08Event regions, delta cycles, blocking versus nonblocking updates, delays, and deterministic testbench timing.
- Simulation scheduling and race avoidance35 min
09Clocks, reset, stimulus, checking, scoreboarding, files, waves, and pass/fail reporting.
- Self-checking Verilog testbenches35 min
10A practical review method for predictable, portable, debuggable RTL.
- RTL coding quality and design review35 min
8-week programme alignment
Verilog · Weeks 2–4
The instructor-led plan develops Verilog through RTL I, RTL II and Verilog Verification before moving to SystemVerilog.
Week 2Verilog RTL I · 2.5 h · 100 marks
Week 3Verilog RTL II · 3.0 h · 100 marks
Week 4Verilog Verification · 3.0 h · 100 marks
What comes next?
Continue from Verilog into SystemVerilog and UVM.
After Weeks 2–4, continue through SystemVerilog language and verification, assertions, functional coverage, UVM and the final integration project.
Continue to Week 5 → Weeks 5–8 · Available