Week 6 · Day 26 · 7 hours

SystemVerilog Verification – Interfaces

interface
modport
clocking blocks
Virtual interface concept
Signal direction and sampling discipline

Concept and setup

Understand what you will build

Day 26 — SystemVerilog Interfaces

Simulation status (28 Oct 2026): run_day26.sh builds and runs both interface examples on Verilator 5.052, and both pass. Icarus Verilog 12 cannot compile these interfaces and modports. Details: Week 6 validation record (VALIDATION.md).

XLS time: theory 2h, guided 2h, independent 2h, debugging 1h.

simple_dut.sv: synchronous DUT.
interface_harness.sv: parameterized interface, DUT and driver/monitor modports, clocking blocks, interface task/function, basic self-check.
virtual_interface_example.sv: class handle to an interface (advanced).
wrong_modport_debug.sv: intentionally wrong direction for debugging; do not compile in normal flow.
LABS.md: all Day 26 lab requirements and the evidence to record for each.
run_day26.sh: builds and runs both examples on Verilator 5 and checks their PASS lines.

The two examples cover the core of the labs; each lab still needs your own code and evidence. Icarus Verilog 12 does not support these interfaces, so use Verilator.

Architecture

Follow the verification data flow

Worked source

Study the supplied implementation

interface_harness.sv

// Illustrative IEEE 1800 SystemVerilog. Simulator support varies.
interface txn_if #(parameter WIDTH=8) (input logic clk);
  logic rst, valid, out_valid;
  logic [WIDTH-1:0] data, result;
  modport DUT(input clk, rst, valid, data, output out_valid, result);
  modport DRIVER(input clk, out_valid, result, output rst, valid, data);
  modport MONITOR(input clk, rst, valid, data, out_valid, result);
  clocking drv_cb @(negedge clk);
    default input #1step output #0;
    output rst, valid, data;
    input out_valid, result;
  endclocking
  clocking mon_cb @(posedge clk);
    default input #1step output #0;
    input rst, valid, data, out_valid, result;
  endclocking
  task automatic clear_bus(); rst=0; valid=0; data='0; endtask
  function automatic bit busy(); return valid && !out_valid; endfunction
endinterface

module interface_harness;
  logic clk=0;
  always #5 clk=~clk;
  txn_if #(.WIDTH(8)) bus(clk);
  simple_dut dut(.clk(clk),.rst(bus.rst),.valid(bus.valid),.data(bus.data),
                 .out_valid(bus.out_valid),.result(bus.result));
  initial begin
    bus.rst=1;bus.valid=0;bus.data=0;
    repeat(2) @(negedge clk);
    bus.rst=0;
    @(negedge clk);bus.valid=1;bus.data=8'd41;
    @(negedge clk);bus.valid=0;
    // Sample after NBA updates to avoid checking the old result.
    #1;
    if (bus.out_valid!==1'b1 || bus.result!==8'd42)
      $fatal(1,"Day26 DUT mismatch");
    $display("DAY26_BASIC_INTERFACE_PASS");
    $finish;
  end
endmodule

simple_dut.sv

// Day 26: one-cycle registered increment; reset is synchronous active-high.
module simple_dut(input logic clk, rst, valid, input logic [7:0] data,
                  output logic out_valid, output logic [7:0] result);
  always_ff @(posedge clk) begin
    if (rst) begin out_valid <= 0; result <= 0; end
    else begin out_valid <= valid; if (valid) result <= data + 8'd1; end
  end
endmodule

virtual_interface_example.sv

// Advanced illustration; requires simulator support for virtual interfaces.
interface control_if(input logic clk);
  logic rst, enable;
  modport DRV(input clk, output rst, enable);
  modport MON(input clk, rst, enable);
endinterface
class control_driver;
  virtual control_if vif;
  function new(virtual control_if vif); this.vif=vif; endfunction
  task drive_reset();
    @(negedge vif.clk); vif.rst=1; vif.enable=0;
    @(negedge vif.clk); vif.rst=0;
  endtask
endclass
module virtual_interface_demo;
  bit clk=0; always #5 clk=~clk;
  control_if bus(clk);
  control_driver driver;
  initial begin
    driver=new(bus); driver.drive_reset();
    if (bus.rst!==0) $fatal(1,"Reset not released");
    $display("DAY26_VIRTUAL_INTERFACE_PASS"); $finish;
  end
endmodule

wrong_modport_debug.sv

// DELIBERATE ERROR: never include this in a normal regression.
interface bad_if(input logic clk);
  logic valid;
  modport BAD_DRIVER(input clk, valid); // BUG: driver cannot write valid.
endinterface
// Fix: modport DRIVER(input clk, output valid);

Guided and independent work

Complete the lab checklist

Day 26 — XLS lab checklist

Each entry stays open until you record your own simulation evidence for it. The supplied examples run on Verilator 5.052 (run_day26.sh).

[ ] Lab 1: Basic interface — Code and demonstrate basic interface with simulation evidence; document observations or debug result.
[ ] Lab 2: Connect interface to DUT — Code and demonstrate connect interface to dut with simulation evidence; document observations or debug result.
[ ] Lab 3: Driver modport — Code and demonstrate driver modport with simulation evidence; document observations or debug result.
[ ] Lab 4: Monitor modport — Code and demonstrate monitor modport with simulation evidence; document observations or debug result.
[ ] Lab 5: Clocking block — Code and demonstrate clocking block with simulation evidence; document observations or debug result.
[ ] Lab 6: Input skew experiment — Code and demonstrate input skew experiment with simulation evidence; document observations or debug result.
[ ] Lab 7: Output skew experiment — Code and demonstrate output skew experiment with simulation evidence; document observations or debug result.
[ ] Lab 8: Parameterized interface — Code and demonstrate parameterized interface with simulation evidence; document observations or debug result.
[ ] Lab 9: Interface task — Code and demonstrate interface task with simulation evidence; document observations or debug result.
[ ] Lab 10: Interface function — Code and demonstrate interface function with simulation evidence; document observations or debug result.
[ ] Lab 11: Multiple interface instances — Code and demonstrate multiple interface instances with simulation evidence; document observations or debug result.
[ ] Lab 12: Virtual-interface handle — Code and demonstrate virtual-interface handle with simulation evidence; document observations or debug result.
[ ] Lab 13: Race-free drive — Code and demonstrate race-free drive with simulation evidence; document observations or debug result.
[ ] Lab 14: Race-free sample — Code and demonstrate race-free sample with simulation evidence; document observations or debug result.
[ ] Lab 15: Wrong-modport debug — Code and demonstrate wrong-modport debug with simulation evidence; document observations or debug result.
[ ] Lab 16: Clocking-direction debug — Code and demonstrate clocking-direction debug with simulation evidence; document observations or debug result.

Debugging assignment

Fix the deliberately incorrect driver modport direction, then refactor a raw-pin testbench to an interface-based harness. Record compile logs and explain the race between Active and NBA regions.

Evidence

Record simulator/version, command, expected and actual results, logs, and PASS/FAIL/BLOCKED for each lab. The supplied examples are starting points, not 100% lab completion.

Assignment and evidence

Demonstrate the required engineering outcome

Debug assignment

Debug wrong modport and clocking direction
Refactor raw-pin TB to interface-based TB

Submission evidence

Source files
README with commands and environment
Lab evidence log and screenshots if applicable
Debug observations and outstanding issues

Review rubric

Source and design: 35
Functional checks: 30
Debug and explanation: 20
Reproducibility: 15

Personal evidence

This lesson is public; no account is needed to study it.

Knowledge check

Confirm the verification concepts

The scored check is being prepared.