Week 6 — SystemVerilog Verification Formal Assessment

Create an interface for a synchronous FIFO with separate driver and monitor modports and a clocking block. Connect it to the DUT and explain sampling versus driving skews.

Marks: 12

Demonstrate a virtual interface handle in a class-based driver. Identify and correct two race or direction errors in a provided or self-created harness.

Marks: 8

Build generator, mailbox, driver, monitor, reference model and scoreboard for the chosen FIFO or timer DUT. Show a full transaction from generation to actual/expected comparison.

Marks: 20

Implement reset, empty, full, boundary and simultaneous-operation tests (where supported by the DUT contract). Inject one controlled mismatch and show that the checker detects it.

Marks: 15

Create a random transaction class using rand/randc, legal ranges, exclusions, inline constraints and pre/post_randomize hooks. Check every randomize() result.

Marks: 15

Extend constraints with if/implication, dist, solve-before, soft preference and a foreach array rule. Show one expected UNSAT case and explain why it fails.

Marks: 10

Submit a complete FIFO or timer verification environment, a short verification plan, and a ten-seed directed-plus-random regression report. Explain coverage gaps and failures.

Marks: 20