Week 2 · Assessment checkpoint

Verilog RTL I

Combinational/sequential/ALU/timer

2.5 hDuration
100Marks
After Day 10Assessment checkpoint
Assessment timing: End of Week 2, after Day 10.
Workbook requirement

Primary deliverable

RTL + TB + waveform

Workbook expectation

Pass expectation

Compiles, simulates, handles corner cases

Assessment detail: Scope, duration, marks, deliverable and pass expectation follow the Week 2 workbook. Question-level tasks are authored for ASIC Campus because the workbook does not provide a complete learner-facing question paper.
Before you start

Verilog RTL I Instructions

  1. Duration: 2.5 hours. Total: 100 marks.
  2. Work individually inside project_workspace/week2_verilog_rtl1/assessment/.
  3. Use synthesizable Verilog for DUT RTL and a Verilog testbench for verification.
  4. All submitted RTL must compile and simulate; preserve logs and waveform evidence.
  5. Use explicit widths and document assumptions for reset, signedness, terminal count and interrupt behavior.
  6. Do not submit waveform evidence without explaining what condition it proves.
100-mark practical assessment

Assessment Questions & Practical Tasks

All tasks stay within the published Week 2 scope: Combinational/sequential/ALU/timer.

QUESTION 1

RTL Fundamentals and Code Analysis

Modules, ports, widths, hierarchy and parameters
15 marks

Answer the written RTL questions and repair a short faulty module containing port, width and undeclared-signal defects.

Requirements
  • Explain net versus procedural variable.
  • Explain continuous assignment and parameter elaboration.
  • Identify at least three defects in the supplied RTL and state their impact.
  • Produce a corrected compiling module.
Evidence to submit

Written answers, faulty/corrected code and compile log.

Marking

Concepts 6; defect identification 4; corrected RTL 5.

QUESTION 2

Combinational RTL Design

MUX/decoder/priority logic and latch avoidance
20 marks

Implement a specified combinational selector/decoder function using clean procedural RTL and verify all required input classes.

Requirements
  • Use blocking assignments in combinational procedural code.
  • Provide complete assignments/default behavior.
  • Include a compact self-checking or exhaustive directed test.
  • Explain why the implementation does not infer a latch.
Evidence to submit

RTL, TB, simulation result and short latch-avoidance explanation.

Marking

Function 10; coding completeness 4; verification 4; explanation 2.

QUESTION 3

Parameterized Arithmetic / ALU

Arithmetic, signedness, shifts and flags
20 marks

Implement or complete a parameterized ALU and demonstrate arithmetic/logic operations plus C/Z/N/V behavior at representative corner cases.

Requirements
  • Parameterize datapath width.
  • Include add/subtract and assigned logic/shift operations.
  • Verify zero, negative, carry and signed-overflow cases.
  • Explain one signedness corner case.
Evidence to submit

ALU RTL, testbench, result log/waveform and flag table.

Marking

Operations 8; flags 6; parameterization 3; corner-case explanation 3.

QUESTION 4

Sequential RTL and Waveform Reasoning

Clocked RTL, reset, enable/load and state
20 marks

Implement a sequential block with reset and control behavior, verify it, and explain the resulting waveform at specified clock edges.

Requirements
  • Use nonblocking assignments for state.
  • Implement the specified reset polarity/type.
  • Verify enable/load/hold behavior.
  • Annotate or describe at least four significant waveform events.
Evidence to submit

RTL, TB, waveform and edge-by-edge explanation.

Marking

Sequential function 9; reset/control correctness 5; waveform evidence 4; explanation 2.

QUESTION 5

Programmable Timer with IRQ

Counter/timer integration and debug
25 marks

Implement a programmable countdown/periodic timer with enable, reload/period value, timeout and IRQ behavior, then verify normal, boundary and reload cases with a self-checking testbench.

Requirements
  • Define terminal-count behavior clearly.
  • Verify reset, enable/hold, reload and timeout.
  • Check at least one minimum/maximum or wrap boundary relevant to the chosen width.
  • Automatically check IRQ assertion timing.
  • Include one debug case or explain an off-by-one failure mode.
Evidence to submit

Timer RTL, self-checking TB, PASS/FAIL log, waveform and brief debug note.

Marking

Timer RTL 10; TB/checking 7; IRQ/boundaries 5; debug/explanation 3.

Submission checklist

Required evidence

  • project_workspace/week2_verilog_rtl1/assessment/
  • All assessed RTL source files
  • Verilog testbench file(s)
  • Compile/simulation PASS/FAIL log
  • Waveform evidence for sequential/timer behavior
  • Written answers, flag table and debug notes
  • README with exact compile/run commands
Completion gate

Pass criteria

  • Total score meets the programme/instructor pass threshold.
  • Required RTL compiles and simulates without manual source correction during evaluation.
  • ALU and timer tests include meaningful corner/boundary cases.
  • Sequential/timer claims are supported by waveform or automated check evidence.
  • Learner can explain the submitted RTL and one debug correction.
Assessment execution contract

2.5-hour submission structure

Workspace: project_workspace/week2_verilog_rtl1/assessment/

Recommended timebox
  1. 0–15 min: read all questions, create workspace and plan test cases.
  2. 15–120 min: implement Q1–Q4 RTL/TB and run directed checks.
  3. 120–140 min: complete Q5 programmable timer with IRQ and boundary tests.
  4. 140–150 min: final regression, evidence check and submission packaging.
Final submission checklist
  • All required Q1–Q5 RTL/testbench/written files are present.
  • logs/assessment.log contains final PASS/FAIL evidence.
  • sim/assessment.vcd or question-specific VCD files are retained.
  • Waveform evidence clearly shows sequential/timer behavior.
  • flag_table.md documents C/Z/N/V expectations.
  • debug_note.md records at least one timer/debug correction.
  • README.md contains exact compile/run commands and a short result summary.
  • No generated executable, unrelated file or Week 3 solution is submitted.
Q1 · 15 marks

RTL Fundamentals and Code Analysis

Required files
  • q1/q1_answers.md
  • q1/fixed_rtl.v
  • q1/tb_q1.v
Mandatory verification
  • Correct syntax/port/width repair
  • Compiles with -Wall
  • At least one automated functional check
Marking rubric
  • Technical answers 6
  • RTL correction 5
  • TB/verification 3
  • Clarity 1
Q2 · 20 marks

Combinational RTL Design

Required files
  • q2/combinational.v
  • q2/tb_combinational.v
Mandatory verification
  • Exercise every legal select/control combination
  • Demonstrate complete output assignment
  • No unintended latch behavior
  • Self-checking PASS/FAIL
Marking rubric
  • RTL correctness 8
  • Complete combinational coding 4
  • TB coverage 5
  • Debug/explanation 3
Q3 · 20 marks

Parameterized Arithmetic / ALU

Required files
  • q3/alu.v
  • q3/tb_alu.v
  • q3/flag_table.md
Mandatory verification
  • Every required ALU opcode
  • Zero and maximum-value boundaries
  • Positive and negative signed overflow
  • Logical/arithmetic shift distinction
  • Independent C/Z/N/V checks
Marking rubric
  • Operations/result 7
  • Parameterization 3
  • C/Z/N/V correctness 5
  • Corner-case TB 4
  • Explanation 1
Q4 · 20 marks

Sequential RTL and Waveform Reasoning

Required files
  • q4/sequential.v
  • q4/tb_sequential.v
  • q4/waveform_notes.md
Mandatory verification
  • Reset assertion/deassertion
  • Enable/hold behavior
  • Load/clear priority
  • At least four annotated clock edges
  • Nonblocking state updates
Marking rubric
  • Sequential RTL 7
  • Reset/control behavior 4
  • TB 4
  • Waveform reasoning 4
  • Coding discipline 1
Q5 · 25 marks

Programmable Timer with IRQ

Required files
  • q5/timer.v
  • q5/tb_timer.v
  • q5/debug_note.md
Mandatory verification
  • Load programmed period
  • One-shot or specified operating mode
  • Exact timeout boundary
  • Automated IRQ assertion timing
  • At least one off-by-one/debug case
Marking rubric
  • Timer RTL 10
  • TB/checking 7
  • IRQ/boundaries 5
  • Debug/explanation 3
Regression commands
iverilog -g2012 -Wall -o sim/assessment.vvp q1/*.v q2/*.v q3/*.v q4/*.v q5/*.v
vvp sim/assessment.vvp | tee logs/assessment.log
gtkwave sim/assessment.vcd
Assessment validity
  • Required assessed RTL cannot compile.
  • No testbench or no meaningful verification evidence is submitted.
  • Submitted design does not correspond to the learner's explained work.
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