Verilog RTL I – Combinational

1. Create project_workspace/week2_verilog_rtl1/day7.
2. Reuse the Day 6 simulation flow.
3. Enable compiler/lint warnings and retain the log.

1. Implement 2:1 MUX using assign, if/else and case.
2. Implement 4:1 and 8:1 MUX blocks.
3. Implement decoder and demultiplexer.
4. Implement encoder and priority encoder.
5. Implement binary-to-one-hot and one-hot-to-binary conversion.
6. Implement min/max selector, leading-one/zero detector and population counter.
7. Create a parameterized MUX and verify representative select/input combinations.

1. Compare continuous assignment with a combinational always block.
2. Why are blocking assignments normally used in combinational procedural RTL?
3. Explain how an incomplete if/case assignment can infer a latch.
4. State the purpose of a default case and when it is required for clear intent.
5. Explain priority behavior in a priority encoder and how it differs from an ordinary encoder.

Correct missing defaults, incomplete output assignments and bad vector slicing in faulty combinational blocks; state what hardware the faulty version could infer.

• combinational RTL library
• testbench/results
• warning-clean compile log
• debug-before/after notes
• written answers

• No unintended latch behavior
• Outputs are assigned for all intended input conditions
• Parameterized MUX verifies correctly
• Debug explanation connects source defect to hardware behavior

• rtl/mux2_assign.v
• rtl/mux2_if.v
• rtl/mux2_case.v
• rtl/mux_n.v
• rtl/decoder.v
• rtl/demux.v
• rtl/priority_encoder.v
• rtl/onehot.v
• rtl/popcount.v
• tb/tb_day7.v

• Every MUX select value
• Decoder/DEMUX legal selections
• Priority encoder multiple-active-input cases
• Binary/one-hot conversion cases
• Population count 0, all-ones and mixed patterns
• Parameterized MUX at two configurations

• All combinational checks PASS
• No unintended latch behavior in reviewed RTL
• No compile errors
• Log and VCD retained