Week 1 · Day 2 · 7 hours

Foundation – Linux/GVim

Linux, GVim, Shell, Digital Design, Basic C++

Open supporting lesson → Week 1 assessment View in full programme
Daily plan

What you will learn and practise

Complete the stages in order and retain the requested evidence.

Theory · 2h

grep/find/sort/uniq/diff/cut/tee
Processes: ps/top/jobs/bg/fg/kill/nohup
Environment variables and PATH
GVim modes, search/replace, tabs, splits, visual block

Guided lab · 2h

1. Extract ERROR/WARNING/PASS/FAIL from logs
2. Find .v/.sv/.log files
3. Compare RTL revisions with diff
4. Edit Verilog in GVim
5. Search/replace signal names

Independent lab · 2h

6. GVim split RTL/TB view
7. Multi-tab editing
8. Visual block column edits
9. Verilog indentation/syntax highlighting
10. Regression log filtering

Debug and assignment · 1h

Create .vimrc for RTL/DV work
Find and correct formatting errors in a sample RTL file

Expected deliverable

.vimrc + GVim-edited RTL/TB files in project_workspace

Practical work

Use Linux text/process tools and GVim efficiently for RTL/DV editing and regression-log inspection.

Setup
  1. Reuse project_workspace from Day 1.
  2. Place sample RTL, TB and log files inside the workspace.
  3. Open files using GVim.
Execution steps
  1. Extract ERROR, WARNING, PASS and FAIL lines with grep.
  2. Locate .v, .sv and .log files with find.
  3. Compare two RTL revisions with diff.
  4. Open RTL/TB in GVim splits and multiple tabs.
  5. Search and replace a signal name safely.
  6. Use visual block editing for a column change.
  7. Create a minimal .vimrc suitable for RTL/DV editing.
Debug challenge

Find and correct formatting problems in the instructor-provided sample RTL file, then show the before/after difference.

Evidence to retain
  • .vimrc
  • edited RTL/TB files
  • filtered regression-log output
  • diff output
Completion criteria
  • GVim split/tab workflow demonstrated
  • Search/replace completed without unintended edits
  • Log filtering produces the requested categories