Week 5 · Assessment brief

Week 5 SystemVerilog Language and OOP — Formal Assessment

150 minutes · 100 marks

Use this read-only assessment for practice and instructor review.

Section A — Collections and data modelling (20 marks)

  1. W5-F-A01 — 8 marks

    Implement a parameterized packet record using typedef struct packed with a 16-bit address, 8-bit payload and 1-bit write flag; show width and casting checks.

  2. W5-F-A02 — 12 marks

    Write a SystemVerilog utility using a queue, dynamic array and associative array to store and count transaction IDs. Demonstrate push/pop, resize, exists and foreach iteration; explain bounds/empty checks.

Section B — Transaction class and OOP (35 marks)

  1. W5-F-B01 — 20 marks

    Implement a transaction class with fields, constructor, display, compare and independent copy methods. Create two objects, modify the copy and prove the original is unchanged.

  2. W5-F-B02 — 15 marks

    Extend a base transaction with read/write subclasses; implement a virtual display/describe method and demonstrate dynamic dispatch through a base handle. Explain deep-copy strategy for a nested object.

Section C — Processes and IPC (35 marks)

  1. W5-F-C01 — 22 marks

    Build a producer-consumer test using a bounded mailbox and a semaphore to guard shared statistics. Produce five transaction IDs, consume exactly five, terminate using a sentinel and print an ordered PASS transcript.

  2. W5-F-C02 — 13 marks

    Demonstrate fork/join, join_any and join_none with a watchdog timeout. Explain event trigger/wait ordering and fix a missed-trigger or hanging-process bug.

Section D — Debugging and evidence (10 marks)

  1. W5-F-D01 — 10 marks

    Diagnose one intentionally broken OOP aliasing example and one IPC deadlock or indefinite wait. Supply minimal before/after changes, expected output, simulator details and reproducible commands.