Look up a concept, code symbol or debugging topic. Continue into the lesson for examples, practice and the next step in your learning path.
Run EDA tools from Python with `subprocess.run`, using argument lists, timeouts and `check`; run many test-and-seed combinations in parallel with `concurrent.futures`; keep each run isolated in its own folder; make random seeds reproducible; and return an exit status that a…
Open reference →Read and write Tcl, the command language used inside many EDA tools; explain Tcl's substitution rules; use variables, lists, dictionaries, `proc`, `foreach`, `if` and `while`; match text with `string` and `regexp`; read and write files; and handle errors with `catch`.
Open reference →Drive Yosys synthesis from a Tcl script with `yosys -c` and `yosys -import`; write timing constraints as Tcl in SDC form with `create_clock`, `set_input_delay` and `set_output_delay`; run static timing with an OpenSTA-style script; make synthesis runs reproducible; and extract the…
Open reference →Read the csh and tcsh setup scripts that many EDA sites and tool vendors still ship; explain the difference between `set` and `setenv`; extend the search path with the `path` array; test for variables with `$?name` and read exit status…
Open reference →Read and write the Perl found in EDA flows: run one-liners that filter and edit files; start every script with `use strict` and `use warnings`; use scalars, arrays and hashes and their sigils; match and capture with regular expressions and…
Open reference →Read and maintain the Perl scripts that run older chip-design flows: recognise common legacy idioms; parse options with `Getopt::Long`; run tools with `system` using a list of arguments and decode `$?` into an exit code; capture tool output safely; generate…
Open reference →Explain the digital abstraction and logic levels; convert among binary, octal, decimal, and hexadecimal; explain positional notation; determine the range of an unsigned value; and recognize extension, truncation, overflow, and wraparound.
Open reference →Interpret two's-complement values; calculate signed range; apply sign extension; reason about fixed-point scale, rounding, and saturation; and explain BCD, Gray code, and parity.
Open reference →Build truth tables; use basic gates and Boolean identities; form canonical SOP and POS expressions; simplify logic with algebra and Karnaugh maps; and explain equivalence, don't-care conditions, hazards, and glitches.
Open reference →Explain and size multiplexers, demultiplexers, encoders, priority encoders, decoders, and comparators; compose larger selection logic; and identify invalid inputs, default behavior, and combinational design defects.
Open reference →Trace half and full adders; distinguish common carry structures; analyze subtraction and width; explain shifters, an ALU, parity, and CRC; and identify loops, incomplete behavior, and delay trade-offs.
Open reference →Distinguish latches from flip-flops; explain synchronous and asynchronous controls; trace registers, shift registers, and counter types; and choose safe clock-enable, reset, and state-retention behavior.
Open reference →Translate requirements into Moore or Mealy state machines; build transition and output tables; compare state encodings; define reachability, recovery, timeout, and safe defaults; and distinguish registered from combinational outputs.
Open reference →Calculate setup slack; distinguish propagation and contamination delay, setup and hold, recovery and removal; explain skew, jitter, uncertainty, and critical paths; and select appropriate reset and clock-domain crossing structures.
Open reference →Compare memory technologies and port arrangements; define read latency and read-during-write behavior; calculate FIFO occupancy and flags; prevent overflow and underflow; and compare fixed-priority with round-robin arbitration.
Open reference →Size signed and unsigned arithmetic; reason about fixed-point rounding, saturation, accumulation, resource sharing, and pipelining; apply request/acknowledge and ready/valid protocols; and calculate latency, throughput, bandwidth, and buffer needs.
Open reference →Define gates, cells, macros, netlists, libraries, PDKs, dies, packages, and PCBs; compare ASIC and FPGA implementation; trace requirements through bring-up; distinguish functional verification from physical sign-off; and explain PVT, power, area, performance, and implementation limits.
Open reference →Explain what Verilog models; distinguish design RTL from testbench code; follow preprocess, compile, elaborate, simulate, synthesize, and timing stages; and run a small design with Icarus Verilog.
Open reference →Use four-state values, nets, procedural variables, sized literals, concatenation, replication, arithmetic, logical, bitwise, reduction, comparison, and shift operators; and predict width and signedness effects.
Open reference →Define modules with clear ports; instantiate hierarchy using named connections; use parameters and localparams; identify unconnected and multiply driven nets; and explain elaboration.
Open reference →Follow the eight-week programme to connect individual concepts with design decisions, simulation, debugging and verification evidence.
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