Verilog purpose and tool flow
Explain what Verilog models; distinguish design RTL from testbench code; follow preprocess, compile, elaborate, simulate, synthesize, and timing stages; and run a small design with Icarus Verilog.
Open reference →VLSI reference library
Look up a concept, code symbol or debugging topic. Continue into the lesson for examples, practice and the next step in your learning path.
Learning references
Clear filters10 references
Values, types, expressions and operators
Use four-state values, nets, procedural variables, sized literals, concatenation, replication, arithmetic, logical, bitwise, reduction, comparison, and shift operators; and predict width and signedness effects.
Open reference →Modules, ports, hierarchy and parameters
Define modules with clear ports; instantiate hierarchy using named connections; use parameters and localparams; identify unconnected and multiply driven nets; and explain elaboration.
Open reference →Continuous assignments and combinational RTL
Model combinational hardware with continuous and procedural assignments; use blocking assignments, defaults, if and case statements; prevent latches; and code decoders, multiplexers, comparators, and ALUs clearly.
Open reference →Clocked RTL, reset and finite-state machines
Model registers with nonblocking assignments; implement enables, counters, and shift registers; distinguish synchronous and asynchronous reset; and code a finite-state machine with safe defaults and recovery.
Open reference →Arrays, memories and generate constructs
Distinguish packed vectors from unpacked arrays; model synchronous memories; define read-during-write behavior; use procedural loops; and create repeated or conditional hardware with generate constructs.
Open reference →Tasks, functions and reusable definitions
Use functions for reusable combinational calculations; use tasks for testbench procedures; choose parameters and localparams for constants; and apply include files and macros without hiding design intent.
Open reference →Simulation scheduling and race avoidance
Explain event-driven simulation, delta cycles, blocking and nonblocking update timing; identify races; separate clock generation, stimulus, and checking; and distinguish simulation delays from implementation timing.
Open reference →Self-checking Verilog testbenches
Build a testbench with a stable clock and reset; apply directed and boundary stimulus; calculate expected results; report useful failures; dump waves; stop cleanly; and return an unambiguous pass/fail outcome.
Open reference →RTL coding quality and design review
Review RTL for functional intent, widths, signedness, combinational completeness, clock and reset discipline, hierarchy, synthesis portability, warnings, X behavior, and verification evidence.
Open reference →Build on what you find
Follow the eight-week programme to connect individual concepts with design decisions, simulation, debugging and verification evidence.
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