Timing, reset and clock-domain crossings
- Calculate setup slack
- Distinguish propagation and contamination delay, setup and hold, recovery and removal
- Explain skew, jitter, uncertainty, and critical paths
- Select appropriate reset and clock-domain crossing structures
source
logic
Explanation
Signals take time to move
Propagation delay is the maximum time from an input change to a valid output. It matters for the latest arrival and setup analysis.
Contamination delay is the minimum time before an output can begin changing. It matters for earliest arrival and hold analysis.
A flip-flop adds clock-to-Q delay before its new output launches into combinational logic.
Setup and hold
For a register-to-register path, data launches from one flip-flop, travels through combinational logic, and must reach the destination in time.
A simplified setup requirement is:
clock period >= launch clock-to-Q(max)
+ combinational delay(max)
+ destination setup time
+ uncertainty adjustment
Setup slack is required arrival time minus actual arrival time. Positive slack meets the analyzed requirement; negative slack is a violation.
Hold checks the earliest data change after the capture edge:
clock-to-Q(min) + contamination delay(min)
must be late enough to satisfy destination hold time and clock relationship
Increasing the clock period can help setup but normally does not fix a same-edge hold violation. Hold is repaired by changing the short data path or clock relationship under the implementation flow.
Clock terms
- Period: time between corresponding clock edges.
- Frequency:
1 / period. - Duty cycle: fraction of a cycle spent high.
- Latency: time for the clock source to reach a sequential element.
- Skew: difference in clock arrival between two points.
- Jitter: edge movement over time.
- Uncertainty: analysis margin covering specified clock variation and modelling effects.
- Critical path: path with the least slack for a given analysis condition.
A 2 ns period corresponds to 500 MHz. Frequency alone does not prove timing; path delays, constraints, corners, and clock behavior determine slack.
Pipelining
Pipelining divides a long combinational path with registers. This can allow a shorter period and higher throughput, but adds latency, state, clock power, and control alignment work. Data, valid bits, tags, and exception information must travel through matching pipeline stages.
Metastability
If an asynchronous signal changes near a sampling edge, a flip-flop may enter a temporary analog state before resolving to 0 or 1. No digital circuit can guarantee zero probability. A synchronizer provides settling time and reduces the probability of metastability escaping into functional logic. Mean time between failures improves with more resolution time and degrades with higher clock and asynchronous-event rates.
Simulation of ideal digital flip-flops does not model analog metastability probability. CDC structure, constraints, tool analysis, and physical implementation matter.
Choosing a CDC method
| Crossing | Typical structure | Reason |
|---|---|---|
| Slowly changing single-bit level | Two or more destination-domain flops | Provides metastability resolution time |
| Narrow pulse | Pulse stretcher, toggle synchronizer, or handshake | Prevents the destination from missing it |
| Multi-bit data held stable | Request/acknowledge handshake | Data remains stable while control crosses |
| Continuous data stream | Asynchronous FIFO | Decouples clocks and preserves words |
| Reset deassertion | Reset synchronizer in each domain | Provides coherent local release |
Synchronizing each bit of a changing bus independently can produce a word that never existed at the source. Gray coding helps pointers because only one bit changes between adjacent values, but every crossing bit still needs a synchronizer and the implementation needs skew constraints.
Reset timing
Recovery and removal are asynchronous-control timing checks analogous to setup and hold around the releasing clock edge. Asynchronous assertion can force state without a clock. Synchronized deassertion prevents different flops in one domain from resuming on different cycles.
Each clock domain needs a documented reset-release method. Reset crossing analysis is related to CDC analysis and should be reviewed with the intended cell library and DFT flow.
Timing is constraint dependent
An unconstrained path can look clean because it was never checked. Timing sign-off requires clocks, generated clocks, I/O delays, exceptions, operating corners, and mode definitions. False paths and multicycle paths are functional claims that need review and verification, not convenient ways to hide violations.
Worked example
A register path has:
- clock period: 4.00 ns;
- launch clock-to-Q maximum: 0.18 ns;
- combinational maximum delay: 3.10 ns;
- destination setup time: 0.22 ns;
- setup uncertainty: 0.15 ns.
Calculate:
data-path requirement = 0.18 + 3.10 + 0.22 + 0.15 = 3.65 ns
setup slack = 4.00 - 3.65 = +0.35 ns
The simplified setup check passes by 0.35 ns. At a 3.33 ns period, slack becomes 3.33 - 3.65 = -0.32 ns, so that timing target fails.
This result applies only to the stated model. Real static timing analysis includes launch/capture clock arrival, edge relationships, derates, variation, and other constraints.
Check yourself
Why can reducing clock frequency help setup but fail to fix hold? Why is a two-flop synchronizer appropriate for a level but insufficient for a changing multi-bit data bus?