Arithmetic datapaths and interfaces

Explanation

Datapath and control

A datapath transforms and stores values through adders, shifters, multipliers, muxes, registers, and memories. Control decides which operation occurs and when data is accepted or committed. Separating them makes widths, timing, states, and verification responsibilities easier to review.

Every datapath signal should have:

• width and signedness;
• numeric format and units;
• legal minimum and maximum;
• valid timing;
• overflow, rounding, and error policy.

Width planning

For full precision:

unsigned N-bit + M-bit: max(N,M)+1 result bits
signed N-bit + M-bit:   max(N,M)+1 bits after compatible extension
unsigned N × M:         N+M product bits
signed N × M:           N+M product bits

A sum of K nonnegative N-bit values may need N + ceil(log2(K)) bits. Signed ranges and coefficient signs need separate bounds analysis.

Never rely only on a typical input. Calculate the worst legal combination, then decide deliberately where narrowing occurs.

Fixed-point rounding and saturation

After multiplication or scaling, a wide intermediate may need fewer fractional or integer bits.

Truncation discards low bits. It is cheap but biased for some distributions.

Round to nearest adds a decision based on discarded bits. Tie behavior, such as ties-to-even or ties-away-from-zero, must be defined.

Saturation clamps above-maximum values to maximum and below-minimum values to minimum. Wraparound retains only low bits. Saturation often suits signal processing and control, while wraparound naturally follows modular counters and addresses.

Accumulators and MAC units

An accumulator adds each new value to stored state. A multiply-accumulate unit calculates acc_next = acc + a*b. Its accumulator is usually wider than one product because repeated additions grow range. Define initialization, number of terms, intermediate precision, final scaling, and overflow policy.

Resource sharing and pipelining

Resource sharing uses one arithmetic unit across operations or cycles. It saves area but adds control, muxing, and latency. Parallel units consume more resources but can raise throughput.

Pipelining inserts registers into a long operation. After filling, a pipeline may accept and produce one item per cycle even when each item's latency is several cycles. Stalls require every pipeline stage and its valid metadata to advance or hold coherently.

Request and acknowledge

A request/acknowledge protocol suits commands or transfers that may take variable time. A safe four-phase level handshake is:

1. requester raises req with stable payload;
2. receiver observes it and raises ack after accepting;
3. requester observes ack and lowers req;
4. receiver observes low req and lowers ack.

Both sides must agree whether back-to-back operations require a low gap and how reset cancels an incomplete exchange.

Ready and valid

The source asserts valid when it presents a real item. The destination asserts ready when it can accept one. Transfer occurs on an active clock edge where both are high.

Core rules:

• The source must keep valid and payload stable while waiting for ready.
• The destination may change ready according to the interface timing rules.
• Neither side may require the other signal to assert before ever asserting its own in a way that deadlocks.
• Each cycle with ready && valid is one transfer, including consecutive cycles.

Deasserting ready applies backpressure. A skid buffer or FIFO may absorb items already in flight.

Registers and peripherals

A memory-mapped register interface must define address, access width, byte enables, reset value, and behavior for:

• read-only and read/write fields;
• write-one-to-clear or write-one-to-set status;
• reserved bits;
• invalid addresses;
• simultaneous hardware and software updates.

Interrupts may be level or pulse based. Level interrupts remain asserted until their cause is cleared and are harder to miss. Timers count a known clock or prescaled tick. PWM controls duty cycle by comparing a counter with a programmed threshold. GPIO needs direction, input sampling, output value, reset, and electrical ownership definitions.

Performance calculations

latency = time from accepted input to corresponding result
throughput = completed items per unit time
bandwidth = transfers/second × useful bits/transfer

A 64-bit interface transferring every cycle at 250 MHz has a theoretical one-direction payload bandwidth of 64 × 250 million = 16 Gbit/s = 2 GB/s. Protocol gaps, headers, backpressure, and implementation limits reduce sustained bandwidth.

Observability

Design useful status: busy, valid, full, empty, error cause, counters, and timeout indication. Observability speeds verification and silicon debug. Avoid clearing evidence before software or a testbench can capture it.

Worked example

A four-tap filter multiplies unsigned 8-bit samples by unsigned 8-bit coefficients and sums four products.

1. Each product needs 16 bits because 255 × 255 = 65025.
2. Four maximum products sum to 260100.
3. Eighteen bits are required because 2^17-1 = 131071 is too small and 2^18-1 = 262143 is sufficient.
4. Four parallel multipliers can accept one sample set per cycle after pipelining.
5. One shared multiplier needs at least four multiply cycles per result, plus accumulation/control overhead.

If the output must return to 8 bits, the specification must define scaling, rounding, and saturation. Simply taking eight low bits would implement modulo arithmetic and can turn a large result into a small one.

Check yourself

Why can a pipeline have five-cycle latency yet one-result-per-cycle throughput? What must a ready/valid source do with its data while valid=1 and ready=0?