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Learning/Knowledge checks/Week 6/Day 26/Check

Module checkpoint

Day 26 · Interfaces knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

6 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 6What is the main verification benefit of a SystemVerilog interface?

It generates random transactions for every connected portIt bundles related signals and access rules into one portIt replaces the DUT ports with class-based transactions

Question 2 of 6What does a modport define?

The physical placement of interface signals on the dieThe clock and reset that every interface user must shareDirections and members visible to one interface user

Question 3 of 6Why use a clocking block in a testbench interface?

To convert interface signals into class membersTo give race-free, synchronized drive and sample timingTo generate the DUT clock from the testbench interface

Question 4 of 6What does a virtual interface stored in a class provide?

A private copy of every interface signal valueA handle to a statically instantiated interfaceA hardware interface created dynamically by the class

Question 5 of 6What is the purpose of clocking-block input skew?

The delay added to the DUT clock before it togglesWhen inputs are sampled relative to the clock eventWhen outputs are driven relative to the clock event

Question 6 of 6A driver cannot assign an interface signal through its modport. What should be checked first?

Whether the driver modport declares the signal as outputWhether the interface was constructed with new in the testWhether the simulator seed allows driving that signal

Review every selection before submitting. You can retry after reading the explanations.

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