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Learning/Knowledge checks/Week 5/Day 21/Check

Module checkpoint

Day 21 · Data Types knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

6 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 6Why can logic represent X while bit cannot?

logic is four-state and bit is two-statelogic is signed and bit is always unsignedlogic is synthesizable and bit is not

Question 2 of 6How does logic [7:0] a differ from logic a[0:7]?

The first is an unpacked array; the second is a packed vectorThe first is a packed vector; the second is an unpacked arrayBoth declare packed vectors with opposite bit ordering

Question 3 of 6What happens when a wider unsigned value is assigned to a narrower destination?

High-order bits are truncatedThe destination automatically growsLow-order bits are always discarded

Question 4 of 6Why should signedness be explicit in arithmetic checks?

Unsigned operands cannot be compared with relational operatorsSigned arithmetic converts X and Z bits to zero firstOne bit pattern has different signed and unsigned values

Question 5 of 6Why is an enum useful for protocol states?

It makes the simulator reject X or Z on the state variableIt automatically generates the next-state transition logicIt names legal values and strengthens type checking

Question 6 of 6When is case equality (===) useful in verification code?

When two real values must be compared with toleranceWhen X and Z bits must be compared explicitlyWhen arithmetic overflow must be ignored

Review every selection before submitting. You can retry after reading the explanations.

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