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VLSI reference library

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Learning references

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Lesson

SystemVerilog data types

Choose between four-state `logic` and two-state `bit`/`int`; declare packed and unpacked arrays correctly; build readable models with `typedef`, `enum` and `struct`; control width and sign with explicit casts; and use `string` for testbench messages.

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Lesson

Dynamic arrays, queues and associative arrays

Select the right collection for a testbench job; size and resize dynamic arrays; use queues as FIFOs and stacks; index sparse data with associative arrays; iterate with `foreach`; and apply the built-in array reduction, ordering and locator methods.

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Lesson

Classes, objects and handles

Declare a class with properties, a constructor and methods; distinguish a handle from the object it refers to; explain `null` handles and garbage collection; implement shallow and deep copies; and use `static` members and `this` correctly.

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Lesson

Processes and inter-process communication

Start parallel threads with `fork...join`, `join_any` and `join_none`; stop threads safely with `disable fork`; synchronise threads with named events; protect shared resources with semaphores; and pass transactions between components with mailboxes.

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Lesson

Interfaces, modports and clocking blocks

Bundle a protocol's signals into an `interface`; restrict direction with `modport`; remove testbench-to-DUT races with a clocking block; connect class-based components to the DUT through a `virtual interface`; and choose input and output skews deliberately.

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Lesson

Layered, transaction-based testbenches

Describe the role of each testbench layer; write transaction, generator, driver, monitor and scoreboard classes; connect them with mailboxes inside an environment; control a run from a test class; and decide when a test has finished.

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Lesson

Constrained randomization

Declare `rand` and `randc` properties; write constraint blocks that keep stimulus legal; call `randomize()` and always check its result; add inline constraints with `randomize() with`; use `pre_randomize` and `post_randomize`; and reproduce a failing test from its seed.

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Lesson

Advanced constraints

Shape value distributions with `dist`; express conditional rules with implication and `if/else`; control solving order with `solve...before`; make defaults overridable with `soft`; switch constraints and random variables on and off at run time; and constrain the size and contents of…

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Lesson

SystemVerilog assertions

Distinguish immediate from concurrent assertions; build sequences with cycle delays and repetition; write properties with overlapping and non-overlapping implication; use `$rose`, `$fell`, `$stable` and `$past`; disable checks during reset; and attach assertions to a design with `bind`.

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Lesson

Functional coverage

Explain the difference between code coverage and functional coverage; write covergroups with coverpoints and explicit bins; mark illegal and ignored values; cross coverpoints to measure combinations; choose when coverage is sampled; and use coverage results to drive test closure.

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Lesson

Integrated verification: a FIFO environment

Combine an interface, class-based components, constrained-random stimulus, a reference model, assertions and coverage into one environment for a synchronous FIFO; organise the run as a regression with recorded seeds; and assemble the evidence needed to sign off a block.

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Build on what you find

Follow the eight-week programme to connect individual concepts with design decisions, simulation, debugging and verification evidence.

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