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Learning/Knowledge checks/Digital Design Fundamentals/Timing, clocking and storage/Check

Module checkpoint

Timing, clocking and storage knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Timing, reset and clock-domain crossings, Memories, FIFOs and arbitration. Read them first if you have not.

6 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 6What does positive setup slack mean?

Data arrives after the setup deadlineThe hold check on that path also passesData arrives before the setup deadline

Question 2 of 6Why is a two-flop synchronizer not sufficient for a multi-bit data bus?

Its flops cannot drive a wide fanout busIt adds two cycles of latency to the dataBits may resolve on different destination cycles

Question 3 of 6What must a FIFO reject or flag when it is empty?

A read requestA reset requestA write request

Question 4 of 6What property does round-robin arbitration improve?

Maximum clock frequency of the arbiterFairness among requesters that keep askingLatency of the highest-priority requester

Question 5 of 6What does negative hold slack indicate?

The clock period must be increased to fix itData arrives too late for the setup checkData changes too soon after the clock edge

Question 6 of 6Why is Gray coding commonly used for asynchronous FIFO pointers?

It lets pointers skip the synchronizersAdjacent counts differ in only one bitIt halves the number of pointer bits

Review every selection before submitting. You can retry after reading the explanations.

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