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Learning/Knowledge checks/Digital Design Fundamentals/Datapaths and implementation/Check

Module checkpoint

Datapaths and implementation knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Arithmetic datapaths and interfaces, ASIC, FPGA and RTL-to-silicon foundations. Read them first if you have not.

6 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 6What happens to throughput after a well-balanced pipeline fills?

It becomes independent of the clockIt must wait for every stage seriallyIt can produce one result each cycle

Question 2 of 6When does a ready/valid transfer occur?

Ready and valid are both high at the edgeValid rises while ready is still lowValid is high for one cycle, ready or not

Question 3 of 6What does synthesis produce from RTL and constraints?

Test vectors and a coverage reportA technology-mapped netlist and reportsA placed-and-routed layout for tapeout

Question 4 of 6Why can an FPGA prototype not prove final ASIC timing?

Its cells, routing and delays differ from the ASICFPGA tools never report timing for a designFPGA timing is always faster than ASIC timing

Question 5 of 6What is backpressure in a ready/valid interface?

The receiver deasserts ready to pause transfersThe receiver drops data it cannot acceptThe sender deasserts valid to pause the receiver

Question 6 of 6Why are timing constraints required during implementation?

Tools cannot judge path timing without themThey supply stimulus for gate-level testsThey replace the RTL as the design source

Review every selection before submitting. You can retry after reading the explanations.

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