Skip to content

ASIC CampusDesign • Verify • Advance

Courses
Training Plan
Reference
Certification
Verify
Login

i

Certificates are generated and issued only to registered learners after the required assessment and technical review. Free public learning content remains available without registration.

Create a free account

Learning/Knowledge checks/Week 6/Day 30/Check

Module checkpoint

Day 30 · Verification Mini Project knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

6 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 6What should a verification plan connect?

Source file names, authors and simulator license countsPhysical routing layers, masks and placement regionsRequirements to scenarios, checks and closure evidence

Question 2 of 6Why should the reference model be independent of the DUT implementation?

An independent model always simulates fasterA copied DUT algorithm can repeat the DUT's own bugThe reference model must also drive the DUT pins

Question 3 of 6What information is essential for reproducing a random regression failure?

Seed, test, tool version, command and failure logThe number of passing tests and total runtimeA waveform screenshot and the final pass count

Question 4 of 6Which FIFO scenarios are essential boundary tests?

Reset deassertion followed by one long random burstA single normal write and read at half occupancyEmpty, full, overflow, underflow, concurrent access, wrap

Question 5 of 6What makes an error-injection test valid?

Any simulator error message is counted as a passThe DUT output is ignored while the fault is activeIt predicts the required error response and checks it

Question 6 of 6What should happen first when one seed fails in a regression?

Keep seed and logs, reproduce alone, then minimizeDelete the failure and rerun only the passing seedsChange the reference model until it matches the DUT

Review every selection before submitting. You can retry after reading the explanations.

ASIC CampusDesign • Verify • Advance

Structured semiconductor design and verification learning with practical engineering exercises, technical review, and verifiable certification.

₹0 course fee • Completely free VLSI training

Learn

All Courses
Linux Fundamentals
Scripting for EDA Automation
Digital Design Fundamentals
Verilog RTL Design
SystemVerilog Design and Verification
8-Week Training Plan
Assignments & Evaluation
How Learning Works

Platform

About
Certification
Verify Certificate
FAQ
Support
Announcements

Policies

Platform Policies
Accessibility

Connect

Academic Partners
Contact Us
support@asiccampus.com

© 2026 ASIC Campus. VLSI Design & Verification training is completely free.Certificates do not constitute employment or placement.