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Learning/Knowledge checks/Verilog RTL Design/Verilog testbench fundamentals/Check

Module checkpoint

Verilog testbench fundamentals knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Self-checking Verilog testbenches. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5What makes a testbench self-checking?

It compares outputs to expected values automaticallyIt dumps a waveform for the engineer to inspectIt reuses the DUT's own outputs as expected values

Question 2 of 5Why should a test end with an explicit pass or fatal result?

Simulators fail any test that ends with $finishAutomation needs an unambiguous outcomeIt is required for $dumpfile to close cleanly

Question 3 of 5What should a directed counter test include besides normal counting?

Many more cycles of normal counting from zeroReset, enable/hold, wraparound and boundary casesRandom stimulus only, so no directed checks

Question 4 of 5What should a scoreboard compare?

Coverage goals against the number of tests runDUT outputs against the previous run's waveformObserved DUT results against independent predictions

Question 5 of 5Why should reset behavior be checked explicitly?

Reset checks replace the need for assertionsA passing reset also proves the clock tree worksWrong initialization can invalidate every later test

Review every selection before submitting. You can retry after reading the explanations.

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