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Learning/Knowledge checks/Verilog RTL Design/Simulation scheduling and race avoidance/Check

Module checkpoint

Simulation scheduling and race avoidance knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Simulation scheduling and race avoidance. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5Why can a testbench race with the DUT on a clock edge?

Same-time-slot process order is undefinedBlocking writes are deferred to the next time stepThe DUT always executes before the testbench

Question 2 of 5When does a nonblocking assignment update its destination?

Later in the same time step, in the NBA regionImmediately, before the next statement executesAt the start of the next simulation time step

Question 3 of 5Why are # delays excluded from ordinary synthesizable RTL?

They model simulator time, not hardware structureSynthesis converts them into chains of buffersThey are only legal inside initial blocks

Question 4 of 5Why can $display immediately after a nonblocking assignment show the old value?

$display output is buffered until the next clockThe destination updates later, in the NBA region$display prints values from the previous time step

Question 5 of 5What is a robust way for a testbench to avoid racing DUT sampling?

Drive and sample at deliberately separated timesUse blocking assignments in every DUT register tooAdd #0 delays before every testbench assignment

Review every selection before submitting. You can retry after reading the explanations.

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