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Learning/Knowledge checks/Verilog RTL Design/Modules, ports, hierarchy, and parameters/Check

Module checkpoint

Modules, ports, hierarchy, and parameters knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Modules, ports, hierarchy and parameters. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5What should connect a child output to its parent?

A parameter of the parent moduleA reg in the parent driven by an always blockA net in the parent, such as a wire

Question 2 of 5Why are named port connections preferred in reviewed RTL?

They are required whenever a module has parametersThey show the intended signal-to-port mappingThey let the tool fix width mismatches for you

Question 3 of 5When does a parameter normally take effect?

During elaborationWhen the first initial block runsAt every clock edge

Question 4 of 5What problem can an implicit positional port connection cause?

Positional ports cannot carry multi-bit vectorsA signal can land on the wrong port if order changesPositional instances cannot override parameters

Question 5 of 5When is localparam preferable to parameter?

When the value must be updated during simulationWhen an internal constant must not be overriddenWhen the constant must be set from each instance

Review every selection before submitting. You can retry after reading the explanations.

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