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Learning/Knowledge checks/Verilog RTL Design/Continuous assignments and combinational RTL/Check

Module checkpoint

Continuous assignments and combinational RTL knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Continuous assignments and combinational RTL. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5What commonly causes an unintended latch in a combinational always block?

Using blocking assignments in always @*An output left unassigned on some pathMixing if and case in the same always block

Question 2 of 5Which assignment style is normally used inside a combinational procedural block?

Continuous assign statementBlocking assignmentNonblocking assignment

Question 3 of 5Why should a combinational case statement define a default or cover all legal values?

So the case statement becomes edge-triggeredSo the case items are checked in parallelSo outputs are defined for every input value

Question 4 of 5Why is always @* safer than a manually written sensitivity list?

It makes the outputs registered on any changeIt includes every signal the block readsIt runs the block only once at time zero

Question 5 of 5What hardware does a conditional operator normally describe in combinational RTL?

A flip-flop regardless of contextSelection logic such as a multiplexerA latch that holds the unselected input

Review every selection before submitting. You can retry after reading the explanations.

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