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Learning/Knowledge checks/Verilog RTL Design/Clocked RTL and state/Check

Module checkpoint

Clocked RTL and state knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Clocked RTL, reset and finite-state machines. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5Which assignment style should normally update registers in a clocked always block?

Blocking assignmentProcedural continuous assignNonblocking assignment

Question 2 of 5Why is a clock enable usually safer than ordinary logic on a clock signal?

It avoids creating an uncontrolled derived clockIt removes the need for a reset on that registerIt turns the register into combinational logic

Question 3 of 5What should an FSM do if its state encoding becomes illegal?

Rely on synthesis to make it unreachableRecover deterministically to a safe stateHold the illegal code until the next reset

Question 4 of 5In a block with q <= d, which value is sampled for q at the active edge?

The value of d at the next falling clock edgeThe value d takes after this edge's updatesThe value d holds at the edge, before updates

Question 5 of 5What must be considered when deasserting an asynchronous reset?

Setup time of the data inputs during resetNothing, since asynchronous reset ignores the clockRecovery/removal timing and synchronized release

Review every selection before submitting. You can retry after reading the explanations.

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