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Learning/Knowledge checks/Verilog RTL Design/Arrays, memories, and generated structure/Check

Module checkpoint

Arrays, memories, and generated structure knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Arrays, memories and generate constructs. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5What does reg [7:0] mem [0:255] describe?

A single 2048-bit packed vector registerAn 8-entry memory with 256-bit entriesA 256-entry memory with 8-bit entries

Question 2 of 5What is a generate loop used for?

Changing module parameters while simulation runsBuilding repeated hardware structure at elaborationRepeating procedural statements every clock edge

Question 3 of 5Why must a memory read-during-write behavior be specified?

Without it the memory cannot be simulated at allDifferent templates may return old or new dataSimulators always return the newly written data

Question 4 of 5What is the difference between a packed vector and an unpacked array?

Packed is one bit field; unpacked is a set of elementsPacked vectors exist only in testbenches; unpacked in RTLPacked is indexed by address; unpacked by bit position

Question 5 of 5Why must a generate-if condition be constant at elaboration?

It selects which hardware structure existsIt is re-evaluated whenever its inputs changeOtherwise it would infer a latch on the branch

Review every selection before submitting. You can retry after reading the explanations.

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