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Learning/Knowledge checks/SystemVerilog Design and Verification/Interfaces, modports and clocking blocks/Check

Module checkpoint

Interfaces, modports and clocking blocks knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Interfaces, modports and clocking blocks. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5What does a modport add to an interface?

Direction and visibility for one user of the interfaceA clock for the interfaceA second copy of every signal

Question 2 of 5What does input #1step in a clocking block do?

Delays the input by one clock cycleDrives the input one step laterSamples the value just before the clock edge

Question 3 of 5How must a clocking-block output be driven?

With a continuous assignWith a nonblocking assignmentWith a blocking assignment

Question 4 of 5How does a class reach DUT signals?

Through a virtual interface handleThrough module ports on the classThrough hierarchical references only

Question 5 of 5What problem does a clocking block remove?

Width mismatches between portsMissing reset valuesRaces between testbench drives and DUT sampling

Review every selection before submitting. You can retry after reading the explanations.

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