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Learning/Knowledge checks/SystemVerilog Design and Verification/SystemVerilog assertions/Check

Module checkpoint

SystemVerilog assertions knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers SystemVerilog assertions. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5When does the consequent of A |=> B start?

One clock cycle after A matchesIn the same cycle A matchesTwo cycles after A matches

Question 2 of 5What does a vacuous pass mean?

The assertion found no clockThe assertion failed silentlyThe antecedent never matched, so nothing was checked

Question 3 of 5What does $past(count) return?

The reset value of countThe value of count one clock cycle earlierThe value of count at time zero

Question 4 of 5What is disable iff (!rst_n) used for?

Ignoring assertion attempts while reset is activeEnabling the assertion only in resetResetting the assertion counter

Question 5 of 5Why attach a checker with bind?

To make the checker synthesizableTo run assertions fasterTo add assertions without editing the RTL file

Review every selection before submitting. You can retry after reading the explanations.

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