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Learning/Knowledge checks/Scripting for EDA Automation/Tcl in EDA tools/Check

Module checkpoint

Tcl in EDA tools knowledge check

Answer every question from your current understanding. After submission, compare your reasoning with the explanation and revisit any weak concept.

This check covers Tcl in EDA tools. Read it first if you have not.

5 QuestionsOne Answer eachImmediate ScoreDetailed Explanations

Read→Reason→Select→Review

Question 1 of 5What does `yosys -import` do inside a Yosys Tcl script?

Makes Yosys commands callable directly as Tcl commandsReads every Verilog file in the current folderLoads the standard-cell library into the design

Question 2 of 5Why must the Yosys `proc` pass still be called as `yosys proc` after importing?

It is only available in the Yosys interactive shellIt needs a Liberty file that import does not loadIts name clashes with the Tcl built-in that defines procedures

Question 3 of 5What does `set_input_delay 2.0 -clock core_clk $ports` tell the timing tool?

The clock reaches those input ports 2 ns lateData on those inputs arrives 2 ns after the clock edgeThose inputs must be held stable for 2 ns after the edge

Question 4 of 5Why is the clock port removed from the list given to set_input_delay?

A clock is not a data input and is already defined by create_clockOpenSTA cannot apply any constraint to a port named clkInput delays may only be set on ports with a bus width above one

Question 5 of 5Why should a report-parsing script fail when it cannot find the expected WNS line?

Timing tools always print their WNS on the very last lineA missing line means the design has no timing paths at allAssuming zero would hide a changed report format or a failed run

Review every selection before submitting. You can retry after reading the explanations.

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